ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 57

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

15 - 10
15 - 6
9 - 3
2 - 0
2 - 0
External Read/Write Address: 031
Bit
External Read Address: 032
Bit
Reset Value: 0000
Reset Value: 0000
15
15
0
5
4
3
0
14
0
14
0
POS6 - 0
SKC2 - 0
Unused
Unused
ST2- 0
Name
Name
SFD
PFD
LMT
13
0
13
0
H
H
12
0
12
0
Table 23 - DPLL Output Adjustment (DPOA) Register Bits
H
Reserved. In normal functional mode, these bits MUST be set to zero.
Phase Offset Bits: These 7 bits form the 2’s complement phase offset word which
controls the DPLL output phase offset. The DPLL output is advanced (leads the refer-
ence) if the word is positive. The DPLL output is delayed (lags the reference) if the
word is negative. The net effect is that the ST-BUS outputs will be advanced or
delayed by the programmed amount.
The offset is in step of 15.2 ns if the input reference is 8 kHz or 2.048 MHz. The offset
is in step of 20.2 ns if the input reference is 1.544 MHz. These bits have no effect in
Freerun or Bypass mode.
Skew Control Bits: These 3 bits control the delay of the DPLL outputs from 0 to
13.3 ns in steps of 1.9 ns. The net effect is that the ST-BUS outputs will be delayed by
the programmed amount. These bits have no effect in Freerun or Bypass mode.
Reserved. In normal functional mode, these bits MUST be set to zero.
Secondary Fail Detection Bit (Read only bit): This bit reports the validity of the
SEC_REF signal. When the secondary reference fails, this bit is set to high.
Primary Fail Detection Bit (Read only bit): This bit reports the validity of the primary
reference signal selected by the P_REFSEL bit in the DOM register. When the
selected primary reference fails, this bit is set to high.
DPLL LIMIT Bit (Read only bit): This bit indicates that the Phase Slope Limiter is
limiting the phase difference between the input reference and the feedback reference.
DPLL State Bits (Read only bit): These bits report the state of the DPLL state
machine. The state numbers are shown in the bubbles in Figure 27 on page 37.
Table 24 - DPLL House Keeping (DHKR) Register Bits
11
0
11
H
0
10
0
10
0
POS6
9
9
0
Zarlink Semiconductor Inc.
POS5
8
ZL50010
8
0
POS4
57
7
7
0
POS3
Description
Description
6
6
0
POS2
SFD
5
5
POS1
PFD
4
4
POS0
LMT
3
3
SKC2
ST2
2
2
SKC1
ST1
Data Sheet
1
1
SKC0
ST0
0
0