ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 15

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

E9, D8, B8,
D9, E8, C8,
PBGA Pin
Number
D12
C12
B14
D7
E7
LQFP Pin
161, 164,
159, 163,
166, 168
165, 167
Number
107
149
148
REF_FAIL0 - 3
Pin Name
OSC_EN
REF0 - 3
OSCo
OSCi
Zarlink Semiconductor Inc.
Oscillator Enable (5 V-Tolerant Input with Internal Pull-down)
If tied high, this pin indicates that there is a 20 MHz external
oscillator interfacing with the device. If tied low, there is no
oscillator and CKi will be used for master clock generation.
If the DPLL is activated, an external oscillator is required and this
pin MUST be tied high.
Oscillator Clock Output (3.3 V Output)
If OSC_EN = ‘1’, this pin should be connected to a 20 MHz crystal
(See Figure 23 on page 104) or left unconnected if a clock
oscillator is connected to OSCi pin under normal operation (See
Figure 24 on page 105).
If OSC_EN = 0, this pin MUST be left unconnected.
Oscillator Clock Input (3.3 V Input)
If OSC_EN = ‘1’, this pin should be connected to a 20 MHz crystal
(See Figure 23 on page 104) or to a clock oscillator under normal
operation (See Figure 24 on page 105).
If OSC_EN = 0, this pin MUST be driven high or low by connecting
either to V
DPLL Reference Inputs 0 to 3 (5 V-Tolerant Schmitt-Triggered
Inputs)
If the device is in Master mode, these input pins accept 8 kHz,
1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz timing references independently. One of these inputs is
defined as the preferred or forced input reference for the DPLL.
The Reference Change Control Register (RCCR) selects the
control of the preferred reference.
These pins are ignored if the device is in slave mode unless
SLV_DPLLEN (bit 13) in the Control Register (CR) is set.
When these input pins are not in use, they MUST be driven high or
low by connecting either to V
Failure Indication for DPLL References 0 to 3 (5 V-Tolerant
Three-state Outputs)
These output pins are used to indicate input reference failure when
the device is in master mode.
If REF0 fails, REF_FAIL0 will be driven high.
If REF1 fails, REF_FAIL1 will be driven high.
If REF2 fails, REF_FAIL2 will be driven high.
If REF3 fails, REF_FAIL3 will be driven high.
If the device is in slave mode, these pins are driven low, unless
SLV_DPLLEN (bit 13) in the Control Register (CR) is set.
ZL50018
15
DD_IO
or to ground.
Description
DD_IO
or to ground.
Data Sheet