ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 37

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

11.0
This device has two main operating modes - Master mode and Slave mode. Each operating mode has different
input/output clock and frame pulse setup requirements and usage.
If the device is programmed to work in Master mode, it is expected that the input clock and frame pulse will be
supplied from the embedded DPLL, either directly using the internal loopback mode or indirectly through external
loopback path. Sources and destinations of the device’s serial input and output data, respectively, have to be
synchronized with the device’s output clock and frame pulse. In Master mode, output clocks and frame pulses are
driven by the DPLL and they are always available with any of the specified frequencies.
The device can also operate in two different Slave modes: Divided Slave mode and Multiplied Slave mode. In either
Slave modes, output clocks and frame pulses are generated based on CKi and FPi. The difference is that, in
Divided Slave mode, the output clocks and frame pulses are directly divided from CKi/FPi, while in Multiplied Slave
mode, the output clocks and frame pulses are generated from an internal high-speed clock synchronized to CKi
and FPi. Therefore, in Divided Slave mode, the output clock rates cannot exceed the CKi rate (the output data rates
are also limited as per Table 1), but in Multiplied Slave mode, all specified output clock rates and data rates are
available on CKo0-3 and STio0-31. The input data rate cannot exceed the CKi rate in either Slave modes, because
input data are always sampled directly by CKi.
By default, CKo4, CKo5 and FPo5 are not available in Slave mode, as the embedded DPLL is disabled. However,
the DPLL can be activated even in Slave mode by programming the SLV DPLLEN bit in the Control Register. When
the DPLL is enabled in Slave mode, CKo4, CKo5 and FPo5 are generated from the DPLL synchronized to one of
the REF0-3 inputs, while the other clocks, frame pulses, and input/output data are synchronized to CKi/FPi. It
basically creates two separate timing domains - one for the DPLL, and one for data switch logic. The two can be
totally asynchronous to each other. In this case the DPLL will be fully functional, including its capability of reference
monitoring.
Note that an external oscillator is required whenever the DPLL is used.
Table 7, “ZL50018 Operating Modes” on page 37 summarizes the different modes of operation available within the
ZL50018. Each Major mode has various associated Minor modes that are determined by setting the relevant Input
Control pins and Control Register bits (Table 18, “Control Register (CR) Bits” on page 55) indicated in the table.
Legend:
X - Don’t care or not applicable.
Reference Lock - Refers to what signal the output pins are locked to:
REF0-3 = Normal Mode
Cki = Bypass. Cki is passed directly through to CKo0-3.
Cki MULT = Cki is passed through clock multiplier to CKo0-3.
* CKi must be phase aligned (edge synchronous) to CKo0-3.
Clock Source - Refers to which clock samples STi and which clock outputs STo; STi applies when STi or STio is input; STo applies when STio is output.
Multiplied
Divided
Master
Major
Slave
Slave
Operating Mode
Device
Device Operation in Master Mode and Slave Modes
Loopback
8/16 M
8/16 M
8/16 M
8/16 M
Minor
CKi
4 M
4 M
4 M
4 M
OSC_EN MODE_4M
1
1
0
1
0
Control
[1:0]
00
11
00
11
00
11
00
11
00
Input Pins
20 MHz 4/8/16 M
20 MHz
20 MHz
OSCi
X
X
Table 7 - ZL50018 Operating Modes
Signal
8/16 M
8/16 M
8/16 M
8/16 M
CKi
4 M
4 M
4 M
4 M
X
Zarlink Semiconductor Inc.
OPM
[1:0]
01
X0
X1
00
11
ZL50018
SLV_DPLLEN
CR Register
37
X
1
0
1
0
Bits
CKi_LP
0
1
X
CKi MULT REF0-3
Freerun, Holdover
CKo0-3
Reference Lock
CKi
or REF0-3
Output Clock Pins
CKo4-5 CKo0-3 CKo4-5
REF0-3
X
X
Yes
Enabled
Yes
Yes
Yes
No
No
Data Sheet
CKi*(
Cko2
CKi
STi
Clock Source
Data Pins
CKo0-3
CKo0-3
(DPLL)
MULT)
Cko2
(CKi)
(CKi
STo