ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 39

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.1
There are four functional modes for the DPLL: normal, holdover, automatic and freerun modes. In addition to these
four functional modes, the DPLL can also be programmed to internal reset mode.
12.1.1
In normal timing mode, the DPLL generates clocks and frame pulses that are phase locked to the active input
reference. Jitter on the input clock is attenuated by the DPLL.
12.1.2
In holdover mode, the DPLL no longer synchronizes the output clock to any input reference. It maintains the
frequency that it was at prior to entering holdover mode. The holdover mode typically happens when the input clock
becomes unreliable or is lost altogether. It takes some time for the system to realize that the input clock is
unreliable. Meanwhile, the DPLL tracks an unreliable clock. Therefore the DPLL could hold to an invalid frequency
when it enters holdover mode. In order to prevent this situation, the DPLL stores the current frequency at regular
intervals in holdover memory so that it can restore the frequency of the input clock just after the input clock became
unreliable.
The accuracy of the output clock with respect to the last valid input clock is subject to certain standards referred to
as Stratum levels where each level requires a certain accuracy. The standards ANSI T1.101 and Telcordia
GR-1244-CORE specify the Stratum level requirements. Where ANSI just gives one total number, Telcordia splits it
into three components, thereby creating a more stringent requirement than ANSI.
In order to meet Stratum 3, the holdover accuracy of the DPLL is better than 0.05 ppm. Note that in order for the
system to meet Stratum 3, the system clock provided by the external oscillator must meet the requirements for the
temperature dependence and drift. If Stratum 3 accuracy is not required, a less stable and cheaper system clock
can be used instead.
12.1.3
In this mode, the state machine controls the DPLL based on the settings in the registers and the quality of the
reference input clocks. The DPLL is internally either in normal or in holdover mode. In the following two sections,
the reference selection and state machine operation in automatic mode will be explained in more details.
12.1.3.1
When the DPLL is programmed to operate in Automatic mode without Preference (RCCR Register, PMS2-0 bits =
000), all references, REF0-3, will have equal importance. A circulating Round Robin selection sequence
determines the reference to be used as shown in Figure 21. The state machine basically searches for valid
reference in a circular order of REF0 -> REF1 -> REF2 -> REF3 -> REF0, etc.
DPLL Timing Modes
Normal Mode
Holdover Mode
Automatic Mode
Automatic Reference Switching Without Preferences
Zarlink Semiconductor Inc.
ZL50018
39
Data Sheet