ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 55

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

23.0
15 - 14
12 - 11
6 - 5
External Read/Write Address: 0000
Reset Value: 0000
Bit
13
10
9
8
7
15
0
Detailed Register Description
14
FPINPOS
CKIN1 - 0
OPM1 - 0
0
DPLLEN
Unused
CKi_LP
CKINP
FPINP
Name
SLV_
DPLLEN
H
SLV_
13
Reserved. In normal functional mode, these bits MUST be set to zero.
DPLL Enable in Slave Mode (ignored in Master Mode)
When this bit is low, DPLL is disabled in Slave mode.
When this bit is high and OSC_EN = 1, the DPLL is enabled in Slave mode.
When SLV_DPLLEN is set in Slave mode, CKo[3:0] and FPo[3:0] are generated from
CKi and FPi. CKo[5:4] and FPo[5] are locked to the selected input reference (one of
REF[3:0]). In this mode of operation, the DPLL retains its functionality, including the
generation of the REF_FAIL[3:0] output signals. See Table 7, “ZL50018 Operating
Modes” on page 37 for more details.
Operation Mode
These bits are used to set the device in Master/Slave operation. Refer to Table 7,
“ZL50018 Operating Modes” on page 37 for more details.
CKi and FPi Loopback (Ignored in Slave mode)
When this bit is low, CKi and FPi are used as input pins.
When this bit is high, CKi and FPi are internally looped back from CKo2 (16.384 MHz)
and FPo2 respectively, and CKi pin and FPi pin should be tied low or high externally;
CKIN1 - 0 (bits 6 - 5) of this register should be programmed to be 00. See Table 7,
“ZL50018 Operating Modes” on page 37 for more details.
Input Frame Pulse (FPi) Position
When this bit is low, FPi straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus)
Clock Input (CKi) Polarity
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
Frame Pulse Input (FPi) Polarity
When this bit is low, the input frame pulse FPi has the negative frame pulse format.
When this bit is high, the input frame pulse FPi has the positive frame pulse format.
Input Clock (CKi) and Frame Pulse (FPi) Selection
The MODE_4M0 and MODE_4M1 pins, as described in “Pin Description” on page 13,
should also be set to define the input clock mode.
OPM
12
1
H
OPM
11
0
Table 18 - Control Register (CR) Bits
CKi_
10
LP
CKIN1 - 0
00
01
10
11
FPIN
POS
Zarlink Semiconductor Inc.
9
ZL50018
CKINP
8
55
FPi Active Period
FPINP
7
Description
122 ns
244 ns
61 ns
CKIN
6
1
Reserved
CKIN
5
0
VAR
EN
4
16.384 MHz
8.192 MHz
4.096 MHz
MBPE
CKi
3
OSB
2
Data Sheet
MS1
1
MS0
0