ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 69

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Reset Value: 16B1
External Read/Write Address: 0042
15 - 0
CFN
Bit
15
15
CFN
14
14
CFN15 - 0
Name
H
CFN
13
13
Table 31 - Centre Frequency Register - Lower 16 Bits (CFRL)
CFN
Center Frequency Number (CFN) Lower 16 Bits: The total binary value of these bits
and the CFRU register bits defines the output center frequency number according to the
following formula:
where, f
clock. For given master clock frequency of 100MHz, and desired output center frequency
of 65.536MHz, the CFN has the value of:
The register contents should be changed only if compensation for input oscillator (or
crystal) frequency offset is required.
e.g. if master clock frequency is off by +20 ppm (100.002 MHz -> 5 times multiplied c20i
of 20.0004 MHz), the CFN should be programmed to be:
The default value of this register SHOULD NOT be changed in any other circumstances.
12
12
H
CFN
11
11
OUT
CFN
is desired output center frequency, while f
CFN
CFN
10
10
=
=
2
26
2
CFN
26
×
9
9
Zarlink Semiconductor Inc.
---------------------------------- -
100.002MHz
×
65.536MHz
65.536MHz
------------------------------ -
ZL50018
100MHz
CFN
8
8
69
CFN
f
7
7
OUT
=
=
Description
2
2
=
26
26
CFN
CFN
----------- -
×
6
6
2
×
26
0.65534689
0.65536
×
CFN
f
MCLK
5
5
=
MCLK
CFN
43980465
=
4
4
43979585
is frequency of DPLL master
CFN
3
3
=
29F16B1
=
CFN
29F1341
2
2
H
Data Sheet
CFN
H
1
1
CFN
0
0