AM79C971KCW AMD [Advanced Micro Devices], AM79C971KCW Datasheet - Page 109

• Manufacturer Part Number: AM79C971KCW
• Manufacturer: AMD [Advanced Micro Devices]

5
4
3
2
1
VGASNOOPVGA Palette Snoop. Read as ze-
MWIEN
SCYCEN
BMEN
MEMEN
errors through the SERR pin and
the SERR bit in the PCI Status
register.
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
ro; write operations have no ef-
fect.
cle Enable. Read as zero; write
operations have no effect. The
Am79C971 controller only gener-
ates Memory Write cycles.
zero; write operations have no ef-
fect. The Am79C971 controller
ignores all Special Cycle opera-
tions.
BMEN enables the Am79C971
controller to become a bus mas-
ter on the PCI bus. The host must
set BMEN before setting the INIT
or STRT bit in CSR0 of the
Am79C971 controller.
and is not effected by S_RESET
or by setting the STOP bit.
The Am79C971 controller will ig-
nore all memory accesses when
MEMEN is cleared. The host
must set MEMEN before the first
memory access to the device.
host must program the PCI Mem-
ory Mapped I/O Base Address
register with a valid memory ad-
dress before setting MEMEN.
For accesses to the Expansion
ROM, the host must program the
PCI Expansion ROM Base Ad-
dress register at offset 30h with a
valid memory address before set-
ting MEMEN. The Am79C971
controller will only respond to ac-
cesses to the Expansion ROM
PERREN
Memory Write and Invalidate Cy-
Special Cycle Enable. Read as
Bus
BMEN is cleared by H_RESET
Memory Space Access Enable.
For memory mapped I/O, the
Master
is
Enable.
cleared
Setting
Am79C971
by
0
PCI Status Register
Offset 06h
The PCI Status register is a 16-bit register that contains
status information for the PCI bus related events. It is
located at offset 06h in the PCI Configuration Space.
Bit
15
IOEN
Name
PERR
when both ROMEN (PCI Expan-
sion ROM Base Address register,
bit 0) and MEMEN are set to 1.
Since MEMEN also enables the
memory mapped access to the
Am79C971 I/O resources, the
PCI Memory Mapped I/O Base
Address register must be pro-
grammed with an address so that
the device does not claim cycles
not intended for it.
MEMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
IOEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
The Am79C971 controller sam-
ples the AD[31:0], C/BE[3:0], and
the PAR lines for a parity error at
the following times:
• In slave mode, during the ad-
dress phase of any PCI bus com-
mand.
• In slave mode, for all I/O, mem-
ory and configuration write com-
mands that select the Am79C971
controller when data is trans-
ferred (TRDY and IRDY are as-
serted).
Am79C971 controller will ignore
all I/O accesses when IOEN is
cleared. The host must set IOEN
before the first I/O access to the
device. The PCI I/O Base Ad-
dress register must be pro-
grammed with a valid I/O address
before setting IOEN.
Description
the Am79C971 controller detects
a parity error.
I/O Space Access Enable. The
Parity Error. PERR is set when
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