AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 187
AM79C978A
Manufacturer Part Number
AM79C978A
Description
Single-Chip 1/10 Mbps PCI Home Networking Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C978A.pdf
(256 pages)
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1 Mbps HomePNA PHY Internal Registers
The registers of the HomePNA PHY are accessible via
the internal MII interface. This interface uses the MII
Control, Address, and Data Registers (BCR32,
HPR0: HomePNA PHY MII Control (Register 0)
Hex
00
Address
Bits
6:0
15
14
13
12
11
10
9
8
7
MII_CONTROL
RESET
Loopback
Speed Selection
Auto-Negotiation Enabled
Power Down
Isolate
Restart Auto-Negotiation
Duplex Mode
Collision Test
Reserved
Mnemonic
Table 61. HPR0: HomePNA PHY MII Control (Register 0)
1 = RESET
0 = Normal operation
** Self Clearing
1 = MII Loopback enabled
0 = MII Loopback disabled
0 = 10 Mbps
1 = Enabled
0 = Disabled
1 = Power down
0 = Normal operation
(This bit is mirrored in PHY Control bit 4)
1 = Electrically isolate PHY from MII
0 = Normal operation
1 = Restart Auto-Negotiation
0 = Normal operation
** Self Clearing
1 = Full-Duplex
0 = Half-Duplex
1 = Enable COL test signal
0 = Disable COL test signal
Write as 0, Ignore Read
Am79C978A
Description
BCR33, and BCR34) in the integrated PCnet controller
to control and communicate to the HomePNA PHY via
the MDC and MDIO signals.
See Table 61 through Table 75.
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Default
Hex
0
0
0
0
0
1
0
0
0
0
Reset
Soft
0
0
0
0
0
1
0
0
0
0
187
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