AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 44

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

Disconnect Without Data Transfer
Figure 19 shows a target disconnect sequence during
which no data is transferred. STOP is asserted on clock
4 without TRDY being asserted at the same time. The
Am79C978A controller terminates the access with the
deassertion of FRAME on clock 5 and of IRDY one
clock cycle later. It finally releases the bus on clock 7.
The Am79C978A controller will again request the bus
after two clock cycles to retry the last transfer. The
starting address of the new transfer will be the address
of the last non-transferred data.
Target Abort
Figure 20 shows a target abort sequence. The target
asserts DEVSEL for one clock. It then deasserts
DEVSEL and asserts STOP on clock 4. A target can
use the target abort sequence to indicate that it can-
not service the data transfer and that it does not want
the transaction to be retr ied. Additionally, the
Am79C978A controller cannot make any assumption
44
DEVSEL
FRAME
TRDY
STOP
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
2
Figure 18. Disconnect With Data Transfer
ADDR i
0111
3
DATA
PAR
4
0000
Am79C978A
DATA
5
PAR
about the success of the previous data transfers in the
current transaction. The Am79C978A controller termi-
nates the current transfer with the deassertion of
FRAME on clock 5 and of IRDY one clock cycle later.
It finally releases the bus on clock 6.
Since data integrity is not guaranteed, the Am79C978A
controller cannot recover from a target abort event.
TheAm79C978A controller will reset all CSR locations
to their STOP_RESET values. The BCR and PCI con-
figuration registers will not be cleared. Any on-going
network transmission is terminated in an orderly se-
quence. If less than 512 bits have been transmitted
onto the network, the transmission will be terminated
immediately, generating a runt packet. If 512 bits or
more have been transmitted, the message will have the
current FCS inverted and appended at the next byte
boundary to guarantee an FCS error is detected at the
receiving station.
6
7
8
9
10
ADDR i +8
0111
11
22399A-21