T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 72

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Ambassador T8110L H.100/H.110 Switch
7 Frame Group and FG I/O
There are eight independently programmable T8110L frame group/FGIO signals, FG[7:0]. In the frame group
mode, the pin is an 8 kHz frame reference output, with programmable pulse width, polarity, and delay offset from
the internally generated frame reference. In the FGIO mode, the pin behaves as a general-purpose register bit,
with programmable direction (IN or OUT) and read masking. The FG7 signal allows for an additional mode of oper-
ation, providing a timer via a 16-bit programmable counter.
Table 57. Frame Group and FG I/O Register Map
7.1 Frame Group Control Registers
7.1.1 FGx Lower and Upper Start Registers
The FGx lower and upper start registers provide a 12-bit delay offset value for the corresponding frame group bit.
Offsets are relative to the T8110L internally generated 8 kHz frame reference and have a resolution down to one
32.768 MHz clock period (30.5 ns increments).
Table 58. FGx Lower and Upper Start Registers
72
Byte Address
DWORD Address
(0x00411)
(0x00421)
(0x00431)
(0x00441)
(0x00451)
(0x00461)
(0x00471)
0x00400
0x00410
0x00420
0x00430
0x00440
0x00450
0x00460
0x00470
0x00401
(20 bits)
0x00400
0x00410
0x00420
0x00430
0x00440
0x00450
0x00460
0x00470
0x00474
0x00480
(FG1 Lower Start)
(FG2 Lower Start)
(FG3 Lower Start)
(FG4 Lower Start)
(FG5 Lower Start)
(FG6 Lower Start)
(FG7 Lower Start)
(FG1 Upper Start)
(FG2 Upper Start)
(FG3 Upper Start)
(FG4 Upper Start)
(FG5 Upper Start)
(FG6 Upper Start)
(FG7 Upper Start)
FG0 Lower Start
FG0 Upper Start
FG7 mode upper
Name
Reserved
FG0 rate
FG1 rate
FG2 rate
FG3 rate
FG4 rate
FG5 rate
FG6 rate
FG7 rate
Byte 3
Bit(s)
7:0
7:0
FG7 mode lower
FGIO R/W
FG0 width
FG1 width
FG2 width
FG3 width
FG4 width
FG5 width
FG6 width
FG7 width
Byte 2
Mnemonic
(F1ULR)
(F2ULR)
(F3ULR)
(F4ULR)
(F5ULR)
(F6ULR)
(F7ULR)
(F1LLR)
(F2LLR)
(F3LLR)
(F4LLR)
(F5LLR)
(F6LLR)
(F7LLR)
F0ULR
F0LLR
LLLL LLLL Lower 8 bits of 12-bit start offset.
0000 LLLL Upper 4 bits of 12-bit start offset.
FG7 counter high byte
Register
Value
FGIO read mask
FG0 upper start
FG1 upper start
FG2 upper start
FG3 upper start
FG4 upper start
FG5 upper start
FG6 upper start
FG7 upper start
Byte 1
Function
FG7 counter low byte
FGIO data register
FG0 lower start
FG1 lower start
FG2 lower start
FG3 lower start
FG4 lower start
FG5 lower start
FG6 lower start
FG7 lower start
Agere Systems Inc.
February 2004
Byte 0