T-8110L AGERE [Agere Systems], T-8110L Datasheet - Page 8

• Manufacturer Part Number: T-8110L
• Manufacturer: AGERE [Agere Systems]

Data Sheet
Ambassador T8110L H.100/H.110 Switch
February 2004
List of Tables
(continued)
Table
Page
Table 51. Watchdog Timer Description .................................................................................................................58
Table 52. Frame Center Sampling ........................................................................................................................59
Table 53. Legacy Mode Fallback Event Triggers ..................................................................................................65
Table 54. Clock Fallback State Description...........................................................................................................67
Table 55. H-Bus Clock Enable State Description..................................................................................................69
Table 56. Clock Failsafe State Descriptions..........................................................................................................71
Table 57. Frame Group and FG I/O Register Map................................................................................................72
Table 58. FGx Lower and Upper Start Registers ..................................................................................................72
Table 59. FGx Width Registers .............................................................................................................................73
Table 60. FGx Rate Registers ...............................................................................................................................73
Table 61. FG7 Counter (Low and High Byte) Registers ........................................................................................74
Table 62. FGIO Data Register...............................................................................................................................75
Table 63. FGIO Read Mask Register ....................................................................................................................75
Table 64. FGIO R/W Register ...............................................................................................................................76
Table 65. GPIO Register .......................................................................................................................................80
Table 66. GPIO Data Register ..............................................................................................................................80
Table 67. GPIO Read Mask Register....................................................................................................................81
Table 68. GPIO R/W Register ...............................................................................................................................81
Table 69. GPIO Override Register ........................................................................................................................82
Table 70. T8110L Serial Stream Groupings..........................................................................................................84
Table 71. H-Bus Rate Registers............................................................................................................................85
Table 72. L-Bus Rate Registers ............................................................................................................................85
Table 73. Interrupt Control Register Map ..............................................................................................................90
Table 74. FGIO Interrupt Pending Registers.........................................................................................................90
Table 75. FGIO Edge/Level and Polarity Registers ..............................................................................................91
Table 76. GPIO Interrupt Pending Register ..........................................................................................................92
Table 77. GPIO Edge/Level and GPIO Polarity Registers ....................................................................................93
Table 78. System Error Interrupt Assignments .....................................................................................................93
Table 79. System Interrupt Pending High/Low Registers......................................................................................94
Table 80. System Interrupt Enable High/Low Registers........................................................................................95
Table 81. Clock Error Interrupt Assignments ........................................................................................................96
Table 82. Clock Interrupt Pending High/Low Registers.........................................................................................97
Table 83. Clock Interrupt Enable High/Low Registers...........................................................................................98
Table 84. Arbitration Control Register ...................................................................................................................99
Table 85. SYSERR Output Select Registers.......................................................................................................100
Table 86. Interrupt In-Service Register ...............................................................................................................101
Table 87. Diagnostics Control Register Map.......................................................................................................106
Table 88. FG Testpoint Enable Registers ...........................................................................................................106
Table 89. FG[7:0] Internal Testpoint Assignments ..............................................................................................107
Table 90. Testpoint Enable Registers .................................................................................................................108
Table 91. GP[7:0] Internal Testpoint Assignments..............................................................................................109
Table 92. State Counter Modes Registers ..........................................................................................................110
Table 93. Miscellaneous Diagnostics Low Register ............................................................................................110
Table 94. Miscellaneous Diagnostic Registers....................................................................................................111
Table 95. Microprocessor Programming, Connection Memory Access ..............................................................113
Table 96. TDM Data Stream ...............................................................................................................................118
Table 97. Subrate Switching, Data Propagation Rate vs. Channel Capacity ......................................................119
Table 98. Subrate Switching, Connection Memory Programming Setup ............................................................120
Table 99. Absolute Maximum Ratings.................................................................................................................124
Table 100. XTAL1 Specifications ..........................................................................................................................124
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