IDT72V90823PQFG IDT, Integrated Device Technology Inc, IDT72V90823PQFG Datasheet - Page 17

• Manufacturer Part Number: IDT72V90823PQFG
• Description: IC DGTL SW 2048X2048 100-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V90823PQFG

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 72V90823PQFG

JTAG SUPPORT
dard IEEE-1149.1. This standard specifies a design-for-testability technique
called Boundary-Scan Test (BST). The operation of the boundary-scan
circuitry is controlled by an external test access port (TAP) Controller.
TEST ACCESS PORT (TAP)
IDT72V90823. It consists of three input pins and one output pin.
any on-chip clock and thus remain independent. The TCK permits shifting of test
data into or out of the Boundary-Scan register cells concurrently with the
operation of the device and without interfering with the on-chip logic.
Controller to control the test operations. The TMS signals are sampled at the
rising edge of the TCK pulse. This pin is internally pulled to Vcc when it is not
driven from an external source.
or into a test data register, depending on the sequence previously applied to
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vcc when it is not driven from an external source.
contents of either the instruction register or data register are serially shifted out
towards the TDO. The data out of the TDO is clocked on the falling edge of the
TCK pulses. When no data is shifted through the boundary scan cells, the TDO
driver is set to a high impedance state.
IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
The IDT72V90823 JTAG interface conforms to the Boundary-Scan stan-
The Test Access Port (TAP) provides access to the test functions of the
•Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with
•Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP
•Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register
•Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the
•Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to VCC.
17
INSTRUCTION REGISTER
public instructions. The IDT72V90823 JTAG Interface contains a two-bit
instruction register. Instructions are serially loaded into the instruction register
from the TDI when the TAP Controller is in its shifted-IR state. Subsequently,
the instructions are decoded to achieve two basic functions: to select the test data
register that may operate while the instruction is current, and to define the serial
test data register path, which is used to shift data between TDI and TDO during
data register scanning. See Table below for Instruction decoding.
TEST DATA REGISTER
test data registers:
arranged to form a scan path around the boundary of the IDT72V90823 core
logic.
path from TDI to its TDO. The IDT72V90823 boundary scan register contains
118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out.
All three-state enable bits are active high.
In accordance with the IEEE 1149.1 standard, the IDT72V90823 uses
Value Instruction
As specified in IEEE 1149.1, the IDT72V90823 JTAG Interface contains two
•The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells
•The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit
000
001
010 Sample/preload
011 Sample/preload
100 Sample/preload
101 Sample/preload
110 Bypass
111 Bypass
EXTEST
EXTEST
JTAG Instruction Register Decoding
COMMERCIAL TEMPERATURE RANGE
Select Boundary Scan Register
Select Boundary Scan Register
Select Boundary Scan Register
Select Boundary Scan Register
Select Boundary Scan Register
Select Boundary Scan Register
Select Bypass Register
Select Bypass Register
Function