IDT72V90823PQFG IDT, Integrated Device Technology Inc, IDT72V90823PQFG Datasheet - Page 4

• Manufacturer Part Number: IDT72V90823PQFG
• Description: IC DGTL SW 2048X2048 100-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V90823PQFG

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 72V90823PQFG

PIN DESCRIPTION
NOTE:
1. These pins are 5V tolerant.
SYMBOL
GND
Vcc
TX0-15
RX0-15
F0i
FE/HCLK
CLK
TMS
TDI
TDO
TCK
TRST
IC
RESET
WFPS
A0-7
DS/RD
R/W / WR
CS
AS/ALE
IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Ground.
Vcc
TX Output 0 to 15
(Three-state Outputs)
RX Input 0 to 15
Frame Pulse
Frame Evaluation/
HCLK Clock
Clock
Test Mode Select
Test Serial Data In
Test Serial Data Out
Test Clock
Test Reset
Internal Connection
Device Reset
(Schmitt Trigger Input)
Wide Frame
Pulse Select
Address 0-7
Data Strobe/Read
Read/Write / Write
Chip Select
Address Strobe or
Latch Enable
NAME
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Ground Rail.
+3.3 Volt Power Supply.
Serial data input stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon
the value programmed at bits DR0-1 in the IMS register.
When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted
according to ST-BUS
pulse which conforms to WFPS formats.
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK
at bits DR0-1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock.
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-
up when not driven.
when not driven.
JTAG scan is not enabled.
Provides the clock to the JTAG test logic.
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V90823 is in the normal functional mode.
Connect to GND for normal operation. This pin must be low for the IDT72V90823 to function normally and to comply
with IEEE 1114 (JTAG) boundary scan requirements.
This input (active LOW) puts the IDT72V90823 in its reset state that clears the device internal counters, registers
reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET
pin must be held LOW for a minimum of 100ns to reset the device.
When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in
ST-BUS
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with CS
to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This
active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus
operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V90823.
This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
Serial data output stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon
the value programmed at bits DR0-1 in the IMS register.
(4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.
Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). Depending upon the value programmed
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up
bus operation, connect this pin to ground.
®
/GCI mode.
®
and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame
4
DESCRIPTION
COMMERCIAL TEMPERATURE RANGE