AM41PDS3224DB100IS AMD [Advanced Micro Devices], AM41PDS3224DB100IS Datasheet
AM41PDS3224DB100IS
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AM41PDS3224DB100IS Summary of contents
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Am41PDS3224D Data Sheet Continuity of Specifications Continuity of Ordering Part Numbers For More Information Publication Number 26085 Revision A Amendment +1 Issue Date May 13, 2003 ...
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PRELIMINARY Am41PDS3224D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29PDS322D 32 Megabit ( 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS ...
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GENERAL DESCRIPTION The Am29PDS322D Mbit, 1.8 V-only Flash memory organized as 2,097,152 words of 16 bits each. The device is designed to be programmed in system with standard system 1 evice ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . ...
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Write Cycle ............................................................................. 52 Figure 30. SRAM Write Cycle—WE# Control ................................. 52 Figure 31. SRAM Write Cycle—CE1#s Control .............................. 53 Figure 32. SRAM Write Cycle—UB#s and LB#s Control ................ 54 Flash Erase And Programming Performance . . 55 Flash Latchup ...
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PRODUCT SELECTOR GUIDE Part Number Standard Voltage Range: V Speed Options = 1.8–2.2 V Max Access Time (ns) CE# Access (ns) OE# Access (ns) Max Page Address Access Time (ns) MCP BLOCK DIAGRAM A20 to A0 A20 to A0 WP#/ACC ...
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FLASH MEMORY BLOCK DIAGRAM A20–A0 RY/BY# A20–A0 RESET# STATE CONTROL WE# & CE# COMMAND REGISTER DQ15–DQ0 A20– Upper Bank Address Upper Bank X-Decoder Status ...
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CONNECTION DIAGRAM LB UB A18 A17 DQ1 ...
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PIN DESCRIPTION A17– Address Inputs (Common) A20–A18 = 3 Address Inputs (Flash Highest Order Address Pin (SRAM) Byte mode DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE1#s = Chip Enable 1 (SRAM) ...
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ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am41PDS322 AMD DEVICE NUMBER/DESCRIPTION Am41PDS3224D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29PDS322D 32 Megabit ( 16-Bit) CMOS 1.8 Volt-only, Simultaneous ...
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MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca ...
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Table 2. Device Bus Operations—SRAM Byte Mode, CIOs = V Operation CE#f CE1#s CE2s OE# WE# (Notes Read from Flash Write to Flash Standby ...
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FLASH DEVICE BUS OPERATIONS Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins control and selects the device. OE# is the output con- trol and ...
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The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V from the ACC pin returns the ...
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Table 4. Am29PDS322DT Top Boot Sector Addresses Sector Address Bank Sector A20–A12 SA0 000000xxx SA1 000001xxx SA2 000010xxx SA3 000011xxx SA4 000100xxx SA5 000101xxx SA6 000110xxx SA7 000111xxx SA8 001000xxx SA9 001001xxx SA10 001010xxx SA11 001011xxx SA12 001100xxx SA13 001101xxx ...
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Table 4. Am29PDS322DT Top Boot Sector Addresses (Continued) Sector Address Bank Sector A20–A12 SA44 101100xxx SA45 101101xxx SA46 101110xxx SA47 101111xxx SA48 110000xxx SA49 110001xxx SA50 110010xxx SA51 110011xxx SA52 110100xxx SA53 110101xxx SA54 110110xxx SA55 110111xxx SA56 111000xxx SA57 ...
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Table 6. Am29PDS322DB Bottom Boot Sector Addresses (Continued) Sector Address Bank Sector A20–A12 SA15 001000xxx SA16 001001xxx SA17 001010xxx SA18 001011xxx SA19 001100xxx SA20 001101xxx SA21 001110xxx SA22 001111xxx SA23 010000xxx SA24 010001xxx SA25 010010xxx SA26 010011xxx SA27 010100xxx SA28 ...
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Table 6. Am29PDS322DB Bottom Boot Sector Addresses (Continued) Sector Address Bank Sector A20–A12 SA63 111000xxx SA64 111001xxx SA65 111010xxx SA66 111011xxx SA67 111100xxx SA68 111101xxx SA69 111110xxx SA70 111111xxx Table 7. Am29PDS322DB Bottom Boot SecSi Sector Address Sector Address A20–A12 ...
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Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection Sector Group Sectors A20–A12 SGA0 SA70 111111XXX SGA1 SA69–SA67 11110XXXX SGA2 SA66–SA63 1110XXXXX SGA3 SA62–SA59 1101XXXXX SGA4 SA58–SA55 1100XXXXX SGA5 SA54–SA51 1011XXXXX SGA6 SA50–SA47 1010XXXXX SGA7 SA46–SA43 1001XXXXX SGA8 SA42–SA39 1000XXXXX ...
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START RESET (Note 1) Perform Erase or Program Operations RESET Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected). 2. All previously protected ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 KBytes in length, and uses a ...
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The system must provide the proper signals to the control pins to prevent unintentional writes when V is greater than V . LKO Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# ...
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The autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read any number of autoselect codes without reinitiating the command sequence. Table ...
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Start 555h/AAh 2AAh/55h 555h/20h XXXh/A0h Program Address/Program Data Data# Polling Device Verify Byte? Yes No Increment Last Address Address ? Yes Programming Completed (BA) XXXh/90h XXXh/00h Figure 3. Unlock Bypass Algorithm The device offers accelerated program operations through the WP#/ACC ...
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When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the ...
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Refer to the Flash Write Operation Status section for information on these status bits. After an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation ...
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Table 10. Am29PDS322D Command Definitions Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Manufacturer ID 4 555 Device ID (Note 9) 4 555 SecSi Sector Factory 4 555 Protect (Note 10) Sector Group ...
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FLASH WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 11 and the following subsec- tions describe the function of these bits. DQ7 ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . – +125 C Ambient Temperature with Power Applied . . . . . . . . ...
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FLASH DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Output Leakage Current LO I ACC Input Leakage Current LIA Flash V Active Inter-Page Read Current ...
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SRAM DC AND OPERATING CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current LO I Operating Power Supply Current Average Operating Current CC1 I s Average Operating Current CC2 V Output Low ...
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FLASH DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 10. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6 Note: Diodes are IN3064 or equivalent Figure 12. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 2.0 V 1.0 V Input 0.0 V Figure 13. Input Waveforms ...
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AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 14. Timing Diagram for Alternating May 13, 2002 Test Setup ...
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FLASH AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t Page Read Cycle PRC t Page Address to Output Delay PACC t t ...
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FLASH AC CHARACTERISTICS A20 CE# OE# WE# High-Z Output May 13, 2002 Same page Addresses PRC ...
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FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width ...
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FLASH AC CHARACTERISTICS Flash Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time (WE# to Address) AVWL AS Address Setup Time to OE ASO Polling ...
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FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE# WE Data RY/BY VCS Notes program address program data ...
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FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data 55h RY/BY# t VCS Notes sector address (for Sector ...
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FLASH AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 21. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t ...
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FLASH AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data ...
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FLASH AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary t RSP Sector/Sector Block ...
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FLASH AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect For sector unprotect, ...
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FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time (WE# to Address) AVWL AS Address Setup Time to CE#f Low During ...
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FLASH AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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SRAM AC CHARACTERISTICS Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time Chip Enable to Output CO1 CO2 t Output Enable Access Time OE t LB#s, UB#s to Access Time BA ...
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SRAM AC CHARACTERISTICS Address CS#1 CS2 UB#, LB# OE# Data Out High-Z Notes CIOs is low, ignore UB#s/LB#s timing and t are defined as the time at which the outputs achieve ...
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SRAM AC CHARACTERISTICS Write Cycle Parameter Description Symbol t Write Cycle Time WC t Chip Enable to End of Write Cw t Address Setup Time AS t Address Valid to End of Write AW t UB#s, LB#s to End of ...
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SRAM AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing measured from CE1#s going low to the end of write. CW ...
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SRAM AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. UB#s and LB#s controlled, CIOs must be high measured from CE1#s going low to the end of write ...
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FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Byte/Word Program Time Chip Program Time Word Mode (Note 3) Notes: 1. Typical program and erase times assume the following conditions 2.0 ...
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SRAM DATA RETENTION Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DR t Data Retention Set-Up Time SDR t Recovery Time RDR Notes: 1. CE1#s V – 0.2 V, CE2s V – 0.2 ...
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PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm May 13, 2002 Am41PDS3224D 57 ...
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REVISION SUMMARY Revision A (February 18, 2002) Initial release. Revision A+1 (May 13, 2002) Distinctive Characteristics Modified text in “High Performance” bullet. Deleted reference to 48-ball FBGA package. Trademarks Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, ...