GS820H32Q-4I GSI [GSI Technology], GS820H32Q-4I Datasheet - Page 5

• Manufacturer Part Number: GS820H32Q-4I
• Description: 64K x 32 2M Synchronous Burst SRAM
• Manufacturer: GSI [GSI Technology]

Mode Pin Functions
Note:
There are pull up devices on LBO and FT pins and a pull down device on and ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Note:
1.
2.
3.
Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1st address
2nd address
3rd address
4th address
Write all bytes
Write all bytes
All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
Byte Write Enable inputs B
All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Write byte
Write byte
Write byte
Write byte
Function
Output Register Control
Read
Read
Power Down Control
Burst Order Control
Mode Name
C
D
A
B
A[1:0]
00
01
10
11
GW
H
H
H
H
H
H
H
L
A[1:0]
A
, B
01
10
00
11
B
, B
C
Pin Name State
and/or B
A[1:0]
BW
10
11
00
01
LBO
H
L
L
L
L
L
L
X
ZZ
FT
D
may be used in any combination with BW to write single or multiple bytes.
A[1:0]
00
01
10
11
H or NC
H or NC
L or NC
H
L
L
B
X
H
L
H
H
H
L
X
A
5/23
B
Standby, I
I
Note: The burst counter wraps to initial state on the 5th clock.
X
H
H
H
H
X
Interleaved Burst
1st address
2nd address
3rd address
4th address
L
L
nterleaved Burst Sequence
B
Flow Through
Linear Burst
Function
Pipeline
Active
DD
= I
GS820H32T/Q-150/138/133/117/100/66
B
X
H
H
H
H
X
L
L
SB
C
A[1:0]
00
01
10
11
B
H
H
H
H
X
L
L
X
D
A[1:0]
01
00
11
10
© 1999, Giga Semiconductor, Inc.
A[1:0]
Notes
2, 3, 4
2, 3, 4
2, 3, 4
10
00
01
11
2, 3
2, 3
1
1
A[1:0]
10
01
00
11
D