GS881Z18T GSI [GSI Technology], GS881Z18T Datasheet
GS881Z18T
Related parts for GS881Z18T
GS881Z18T Summary of contents
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... NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc. Functional Description The GS881Z18/36T is an 8Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles ...
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... GS881Z18T Pinout 100 DDQ DDQ DDQ ...
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GS881Z36T Pinout 100 DDQ ...
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TQFP Pin Descriptions Pin Location Symbol 37 35, 34, 33, 32, 100, 99, 83, 82 81, 50, 49, 48, 47, 46, 45 ...
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Pin Location Symbol 38 TMS 39 TDI 42 TDO 43 TCK V 15, 41, 65, 91 5,10, 17, 21, 26, 40, 55, 60, 67, V 71, 76 11, 20, 27, 54, 61, 70, 77 DDQ 16 DP ...
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... GS881Z18/36 ByteSafe NBT SRAM Functional Block Diagram Rev: 1.10 8/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Amps Sense Drivers Write 6/34 Preliminary . GS881Z18/36T-11/100/80/66 © 1998, Giga Semiconductor, Inc. ...
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... A B Cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
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... Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active Write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write cycles. 4. ...
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Pipeline and Flow Through Read-Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition for ...
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Pipeline Mode Data I/O State Diagram Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.10 8/2000 Specifications cited ...
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Flow Through Mode Data I/O State Diagram B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.10 8/2000 Specifications cited are subject to ...
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... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
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... ByteSafe™ Parity Functions This SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are reported one clock cycle later ...
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Write Parity Error Output Timing Diagram Rev: 1.10 8/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com tKQ tHZ tKQX tLZ ...
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Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage Voltage in V DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V Voltage on Other ...
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... Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper- ature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1 ...
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AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
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Operating Currents Parameter Test Conditions Device Selected; Operating All other inputs Current IH IL Output open Standby ZZ V – 0 Current Device Deselected; Deselect All other inputs Current Rev: ...
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AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow- through Clock to Output Invalid Clock to Output in Low-Z Clock ...
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Pipeline Mode Read/Write Cycle Timing CKE ADV – – Write Write COMMAND D(A2) D(A1) ...
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Pipeline Mode No-Op, Stall and Deselect Timing CKE ADV – Write D(A1) COMMAND *Note High (False ...
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Flow Through Mode Read/Write Cycle Timing CKE ADV – D(A1 Write COMMAND D(A1) *Note High ...
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Flow Through Mode No-Op, Stall and Deselect Timing CKE ADV W Bn – Write COMMAND D(A1) *Note High (False ...
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JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but does not implement all of the functions required for ...
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Boundary Scan Register Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found ...
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Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions not 1194.1- compliant because some of the mandatory ...
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Register. Because the RAM clock is independent from the TAP Clock (TCK possible for the TAP to attempt to capture the I/O ring con- tents while the input buffers are in transition (i. metastable state). Although ...
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JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Test Port Input High Voltage Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output ...
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JTAG Port Timing Diagram tTKH tTKL TCK TMS TDI TDO tTKQ JTAG Port AC Electrical Characteristics Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI ...
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GS881Z18/36T TQFP Boundary Scan Register Order x36 x18 Pin n n ...
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Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 0.0 -20.0 -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0 Rev: 1.10 8/2000 Specifications cited are subject to change without notice. For ...
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TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...
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... GS881Z18T-80 512K x 18 GS881Z18T-66 256K x 36 GS881Z36T-11 256K x 36 GS881Z36T-100 256K x 36 GS881Z36T-80 256K x 36 GS881Z36T-66 512K x 18 GS881Z18T-11I 512K x 18 GS881Z18T-100I 512K x 18 GS881Z18T-80I 512K x 18 GS881Z18T-66I 256K x 36 GS881Z36T-11I 256K x 36 GS881Z36T-100I 256K x 36 GS881Z36T-80I 256K x 36 GS881Z36T-66I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “ ...
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Types of Changes DS/DateRev. Code: Old; Format or Content New GS881Z18/36TRev1.04h 5/ 1999; 1.05 9/1999 GS881Z18/36T 1.05 9/ 1999K/ 1.06 10/1999 GS881Z18/36T 1.06 9/ 1999K 1.07 1/2000L Rev.1.08; 881Z18_r1_09 881Z18_r1_09; 881Z18_r1_10 Rev: 1.10 8/2000 Specifications cited are subject to change ...