GS881Z18T GSI [GSI Technology], GS881Z18T Datasheet - Page 25

• Manufacturer Part Number: GS881Z18T
• Description: 8Mb Pipelined and Flow Through Synchronous NBT SRAMs
• Manufacturer: GSI [GSI Technology]

Boundary Scan Register
Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary
Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins
and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the
control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then
is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP instructions can be used to
activate the Boundary Scan Register.
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
Rev: 1.10 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
JTAG TAP Block Diagram
Bit #
x36
x18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
X
X
Revision
X
X
Code
Die
X
X
X
X
TDI
TMS
TCK
0
0
0
0
0
0
0
0
0
0
Not Used
0
0
Test Access Port (TAP) Controller
Bypass Register
Instruction Register
ID Code Register
Boundary Scan Register
31 30 29
2
0
n
0
0
1
· · ·
0
0
0
25/34
·
0
0
· · ·
· · ·
0
0
0
0
2
· · ·
1
0
0
0
0
0
Configuration
2
1
0
0
0
I/O
0
1
1
1
0
0
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
GS881Z18/36T-11/100/80/66
GSI Technology
JEDEC Vendor
© 1998, Giga Semiconductor, Inc.
TDO
ID Code
Preliminary
0
1
1
.