EMC6D103-CK SMSC [SMSC Corporation], EMC6D103-CK Datasheet - Page 47

• Manufacturer Part Number: EMC6D103-CK
• Description: FAN CONTROL DEVICE WITH HIGH FREQUENCY PWM
• Manufacturer: SMSC [SMSC Corporation]

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
SMSC EMC6D103
7.1.4.9
7.1.4.10
7.1.5
FREQUENCY
PWM
(HZ)
21.9
14.6
11
Note 7.4
Note 7.5
Detection of a Stalled Fan
There is a fan failure bit (TACHx) in the interrupt status register used to indicate that a slow or stalled
fan event has occurred. If the tach reading value exceeds the value programmed in the tach limit
register the interrupt status bit is set. See Interrupt Status register 2 at offset 42h.
Notes:
■
■
■
Fan Interrupt Status Bits
The status bits for the fan events are in Interrupt Status Register 2 (42h). These bits are set when the
reading register is above the tachometer minimum and the Interrupt Enable 2 (Fan Tachs) register bits
are configured to enable Fan Tach events. No interrupt status bits are set for fan events (even if the
fan is stalled) if the associated tachometer minimum is set to FFFFh (registers 54h-5Bh).
Note: The Interrupt Enable 2 (Fan Tachs) register at offset 80h defaults to enabled for the individual
See
Linking Fan Tachometers to PWMs
The TACH/PWM Association Register at offset 81h is used to associate a Tachometer input with a
PWM output. This association has three purposes:
1. The auto fan control logic supports a feature called SpinUp Reduction. If SpinUp Reduction is
The reading register will be forced to FFFFh if a stalled event occurs (i.e., stalled event =no edges
detected.)
The reading register will be forced to either FFFFh or FFFEh if a slow fan event occurs. (i.e., slow
event: 0 < #edges < programmed #edges). If the control bit, SLOW, located in the TACHx Options
registers at offsets 90h - 93h, is set then FFFEh will be forced into the corresponding Tach Reading
Register to indicate that the fan is spinning slowly.
The fan tachometer reading register stays at FFFFh in the event of a stalled fan. If the fan begins
to spin again, the tachometer logic will reset and latch the next valid reading into the tachometer
reading register.
enabled (SUREN bit), the auto fan control logic will stop driving the PWM output high if the
associated TACH input is operating within normal parameters. (Note: SUREN bit is located in the
Configuration Register at offset 7Fh)
Figure 6.1 Interrupt Controlon page
Table 7.3 Minimum RPM Detectable Using 2 Edges (continued)
(MSEC)
tachometer status events bits. The group Fan Tach INT# bit defaults to disabled. This bit needs
to be set if Fan Tach interrupts are to be generated on the external INT# pin.
17.12
22.73
11.42
25%
PULSE WIDTH AT DUTY CYCLE
100% duty cycle is 255/256
RPM=60/T
2*(PWM ”ON” Time-Guard Time). Minimum RPM values shown use minimum guard time
(88.88usec).
(PWM ”ON” TIME)
(MSEC)
Revolution
22.83
34.25
45.45
50%
, T
TachPulse
DATASHEET
(Note
(MSEC)
100%
45.48
68.23
90.55
27.
= T
47
7.4)
Revolution
MINIMUM RPM AT DUTY CYCLE
/2. Using 2 edges for detection, T
1324
25%
881
663
(30/T
50%
660
TachPulse
439
331
Revision 0.4 (04-04-05)
)
(Note
100%
330
220
166
TachPulse
7.5)
=