EMC6D103-CK SMSC [SMSC Corporation], EMC6D103-CK Datasheet - Page 73

• Manufacturer Part Number: EMC6D103-CK
• Description: FAN CONTROL DEVICE WITH HIGH FREQUENCY PWM
• Manufacturer: SMSC [SMSC Corporation]

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
SMSC EMC6D103
8.2.22
8.2.23
8.2.24
8.2.25
Register
Address
Register
Address
Register
Address
Register
Address
7Ah
7Ch
7Bh
79h
Read/
Read/
Write
Write
R/W
Read/
Read/
Write
Write
R/W
R
R/W
■
■
Since the test mode is XOR tree, the order of the signals in the tree is not important. SDA and SCL
are not included in the test tree.
Register 79h: SMSC Test Register
This is a read/write register. Writing this register may produce unwanted results.
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
Register 7Ah: SMSC Test Register
This is a read/write register. Writing this register may produce unwanted results.
Register 7Bh: SMSC Test Register
This is a read/write register. Writing this register may produce unwanted results.
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
Register 7Ch: Special Function Register
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
TACH1, TACH2, TACH3, TACH4
PWM2, PWM3
Special Function
Register Name
SMSC Test Register
Register Name
SMSC Test Register
SMSC Test Register
Register Name
Table 8.42 Register 7Ch: Special Function Register
Register Name
Table 8.40 Register 7Ah: SMSC Test Register
Table 8.41 Register 7Bh: SMSC Test Register
Table 8.39 Register 79h: SMSC Test Register
(MSb)
AVG2
Bit 7
AVG1
Bit 6
(MSb)
Bit 7
RES
(MSb)
TST7
Bit 7
DATASHEET
(MSb)
TST7
Bit 7
AVG0
Bit 5
TST6
Bit 6
TST6
Bit 6
73
TST6
Bit 6
SMSC
Bit 4
TST5
Bit 5
TST5
Bit 5
TST5
Bit 5
TST4
Bit 4
TST4
Bit 4
SMSC
TST4
Bit 4
Bit 3
TST3
Bit 3
TST3
Bit 3
TST3
Bit 3
INTEN
Bit 2
TST2
TST2
Bit 2
Bit 2
TST2
Bit 2
MONMD
Bit 1
TST1
TST1
Bit 1
TST1
Bit 1
Bit 1
Revision 0.4 (04-04-05)
LPMD
(LSb)
(LSb)
TST0
(LSb)
Bit 0
TST0
(LSb)
Bit 0
TST0
Bit 0
Bit 0
Default
Default
Default
Default
Value
Value
Value
Value
00h
00h
00h
40h