EMC6D103-CK SMSC [SMSC Corporation], EMC6D103-CK Datasheet - Page 84

• Manufacturer Part Number: EMC6D103-CK
• Description: FAN CONTROL DEVICE WITH HIGH FREQUENCY PWM
• Manufacturer: SMSC [SMSC Corporation]

Revision 0.4 (04-04-05)
9.2
Fsmb
Tsp
Tbuf
Thd:sta
Tsu:sta
Tsu:sto
Thd:dat
Tsu:dat
Tlow
Thigh
Tf
Tr
C
SYMBOL
b
SDA
SCLK
P
Note 9.3
Note 9.4
Note 9.5
SMBus Interface
t
BUF
SMB Operating Frequency
Spike Suppression
Bus free time between Stop and Start
Condition
Hold time after (Repeated) Start Condition.
After this period, the first clock is
generated.
Repeated Start Condition setup time
Stop Condition setup time
Data hold time
Data setup time
Clock low period
Clock high period
Clock/Data Fall Time
Clock/Data Rise Time
Capacitive load for each bus line
S
t
The SMBus timing (e.g., max clock frequency of 400kHz) specified exceeds that specified
in the System Management Bus Specification, Rev 1.1. This corresponds to the maximum
clock frequency for fast mode devices on the I
version 2.0, Dec. 1998.
At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input
filter.
If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns
(1000 ns (T
HD;STA
t
LOW
PARAMETER
t
HD;DAT
Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
R
max) + 250 ns (T
t
R
Figure 9.2 SMBus Timing
Table 9.2 SMBus Timing
t
HIGH
DATASHEET
84
SU
t
SU;DAT
:
DAT
t
10
1.3
0.6
0.6
0.6
0.3
100
1.3
0.6
20+0.1C
20+0.1C
F
t
SU;STA
min) @ 100 kHz) before the SCLK line is released.
MIN
LIMITS
b
b
S
2
C bus. See “The I
MAX
t
400
300
300
400
0.9
HD;STA
50
UNITS
kHz
ns
µs
µs
µs
µs
µs
µs
µs
pF
ns
ns
ns
2
C Bus Specification,”
t
SU;STO
SMSC EMC6D103
COMMENTS
Note 9.3
Note 9.4
Note 9.5
Datasheet
P