ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 40

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 18. Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
If the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in
Figure 19 can be used. The figure shows TSYS_CLK_AC being sourced by TCK78A and TSYS_CLK_AD being
sourced by TCK78A/2 (the division is done in FPGA logic). Similar clocking would be used for Block B.
Figure 19. Mixed Rate Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
Receive Clock Source Selection and Recommended Clock Distribution
In the receive path, one clock per block of two channels, called RCK78[A:B], is sent to the FPGA logic. The control
register bits RCKSEL[A:B] is used to select the clock source for these clocks. The selection of the source for
RCK78[A:B] is controlled by this bit as shown in Table 15.
Table 15. RCK78[A:B] Source Selection
In the receive channel alignment bypass mode the data and recovered clocks for the four channels are indepen-
dent. The data for each channel are synchronized to the recovered clock from that channel.
Figure 21 shows the recommended receive clocking for a single block.
All Clocks at
78.125 MHz
FPGA
FPGA
Logic
Logic
25 MHz
50 MHz
÷
2
Channel AC Selected
as Clock Source
TSYS_CLK_AC
TSYS_CLK_AD
TSYS_CLK_AC
TSYS_CLK_AD
TCK78A
TCK78A
RCKSEL[A:B]
Common Logic, Block A
Common Logic, Block A
0
1
Channel AC
Channel AD
Channel AC
Channel AD
40
ORCA ORT42G5 and ORT82G5 Data Sheet
Clock Source
Channel C
Channel D
2
2
Outgoing Serial Data
Two Channels of
Outgoing Serial Data
2.0 Gbps (Full-Rate)
and One Channel of
1.0 Gbps (Half-Rate)
3.125 Gbps
REFCLK[P:N]_A
156.25 MHz
REFCLK[P:N]_A
100 MHz
One Channel of