ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 54

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Parallel Loopback at the SERDES Boundary
In this parallel loopback differential data are received at the HDINP_xx and HDINN_xx pins and are retransmitted
at the HDOUTP_xx and HDOUTN_xx pins. The loopback path is at the interface between the SERDES blocks and
the MUX and DEMUX blocks and uses the parallel 10-bit buses at these interfaces (see Figure 32b). The loopback
connection is made such that the input signals to the TX SERDES block is the same as the output signals from the
RX SERDES block. In this parallel loopback mode, the MRWDxx[39:0] signal lines remain active and the
TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal lines are not used. This mode is normally used for tests
where serial test data is received from and transmitted to either test equipment or via a serial backplane to a
remote card and is the basic loopback path shown earlier in Figure 32(b).
The data rate selection bits TXHR and RXHR in the channel configuration registers must be configured to carry the
same value. Also, the 8b/10b encoder and decoder are excluded from the loopback path by setting the 8b10bT and
8b10bR configuration bits to 0. Table 21 and Table 22 illustrate the control interface register configuration for the
parallel loopback.
Table 21. Parallel Loopback at the SERDES Boundary Configuration Bit Definitions
Table 22. Parallel Loopback at the SERDES Boundary Configuration Bit Definitions for the ORT82G5
30801, 30901
*This test mode can also be set using TESTEN_xx in place of LOOPENB_xx. In that case, Test Mode must be set to 00000.
30002, 30012,
30022, 30032,
30102, 30112,
30122, 30132
30003, 30013,
30023, 30033,
30103, 30113,
30123, 30133
30005, 30105
30006, 30016,
30026, 30036,
30106, 30116,
30126, 30136
30022, 30032,
30122, 30132
30023, 30033,
30123, 30133
30005, 30105
30026, 30036,
30126, 30136
Address (Hex)
Address (Hex)
Register
Register
Register
Address
Bit 0 = 0 or 1
Bit 0 = 0 or 1
Bit 0 = 0 or 1
Bit 7 = 0
Bit 0 = 0 or 1
Bit 3 = 0
Bit 7 = 1
Bits[4:0]
Bit Value
Bit 7 = 0
Bit 3 = 0
Bit 7 = 1
Bits[4:0]
Bit Value
Bit 2 = 1 (Channel C)
Bit 3 = 1 (Channel D)
Bit 1 = 1 (Channel B)
Bit 0 =1 (Channel A)
Bit Value
GTESTEN
Bit Name
Testmode
8b10bR
8b10bT
TXHR
RXHR
GTESTEN
Bit Name
Testmode
8b10bR
8b10bT
RXHR
TXHR
LOOPENB_xx Set any of the bits 0-3 to 1 to do serial loopback on the corre-
Bit Name
Set to 0 or 1. TXHR and RXHR bits must be set to the same value.
Set to 0 The 8b/10b encoder is excluded from the loopback path. The
8b/10b encoder and decoder selection control bits must both be set to 0.
Set to 0 or 1. TXHR and RXHR bits must be set to the same value.
Set to 0.The 8b/10b decoder is excluded from the loopback path. The
8b/10b encoder and decoder selection control bits must both be set to 0.
SET to 1 if the loopback is done globally on all four channels.
Set to 00001
Set to 0 or 1. TXHR and RXHR bits must be set to the same value.
Set to 0 The 8b/10b encoder is excluded from the loopback path. The
8b/10b encoder and decoder selection control bits must both be set to 0.
Set to 0 or 1. TXHR and RXHR bits must be set to the same value.
Set to 0.The 8b/10b decoder is excluded from the loopback path. The
8b/10b encoder and decoder selection control bits must both be set to 0.
SET to 1 if the loopback is done globally on both channels.
Set to 00001
54
sponding channel.* The high speed serial outputs will not be
active.
ORCA ORT42G5 and ORT82G5 Data Sheet
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