ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 43

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Internal Clock Signals at the FPGA/Core Interface for the ORT82G5
There are several clock signals defined at the FPGA/Embedded Core interface in addition to the external reference
clock for each SERDES quad. All of the ORT82G5 clock signals are shown in Figure 24 and are described follow-
ing the figure.
Figure 24. ORT82G5 Clock Signals (High Speed Serial I/O Also Shown)
REFCLKP_[A:B], REFCLKN_[A:B]:
These are the differential reference clocks provided to the ORT82G5 device as described earlier. They are used as
the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbps, the reference clocks
will be at a frequency of 156.25 MHz.
RWCK[AA:BD]:
These are the low-speed receive clocks from the embedded core to the FPGA across the core-FPGA interface.
These are derived from the recovered low-speed complementary clocks from the SERDES blocks. RWCK_AA
belongs to Channel AA, RWCK_AB belongs to channel AB and so on. With a reference clock input of 156.25 MHz,
these clocks operate at 78.125 MHz.
RCK78[A:B]:
These are muxed outputs of RWCKA[A:D] and RWCKB[B:D] respectively. With a reference clock input of 156.25
MHz, these clocks operate at 78.125 MHz.
FPGA
Logic
TSYS_CLK_AA
TSYS_CLK_AB
TSYS_CLK_AD
TSYS_CLK_BC
RSYS_CLK_A1
RSYS_CLK_B1
RSYS_CLK_B2
TSYS_CLK_BD
TSYS_CLK_AC
RSYS_CLK_A2
TSYS_CLK_BA
TSYS_CLK_BB
RWCKAA
RWCKAB
RWCKAC
RWCKAD
RWCKBA
RWCKBC
RWCKBD
RWCKBB
RCK78A
TCK78A
TCK78A
RCK78B
TCK78B
Common Logic, Quad A
Common Logic, Quad B
Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
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ORCA ORT42G5 and ORT82G5 Data Sheet
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REFCLK[P:N]_A
HDIN[P:N]_AA
HDOUT[P:N]_AA
HDIN[P:N]_AB
HDOUT[P:N]_AB
HDIN[P:N]_AC
HDOUT[P:N]_AC
HDIN[P:N]_AD
HDOUT[P:N]_AD
REFCLK[P:N]_B
HDIN[P:N]_BA
HDOUT[P:N]_BA
HDIN[P:N]_BB
HDOUT[P:N]_BB
HDOUT[P:N]_BC
HDIN[P:N]_BD
HDOUT[P:N]_BD
HDIN[P:N]_BC
Backplane
Serial
Link