ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 61

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), xx = [AC, AD, BC or BD]
30022 - AC
30032 - AD
30122 - BC
30132 - BD
30023 - AC
30033 - AD
30123 - BC
30133 - BD
Absolute
Address
(0x)
[5:7] Not used
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
TXHR_xx
PWRDNT_xx
PE0_xx
PE1_xx
HAMP_xx
Reserved
Reserved
8b10bT_xx
RXHR_xx
PWRDNR_xx
Reserved
8b10bR_xx
LINKSM_xx
Name
Reset
Value
(0x)
00
20
Transmit Half Rate Selection Bit, Channel xx. When TXHR_xx = 1,
HDOUT_xx's baud rate = (REFCLK[A:B]*10) and TCK78[A:B] =(REF-
CLK[A:B]/4); when TXHR_xx=0, HDOUT_xx's baud rate = (REF-
CLK[A:B]*20) and TCK78[A:B]=(REFCLK[A:B]/2). TXHR_xx = 0 on
device reset.
Transmit Powerdown Control Bit, Channel xx. When PWRDNT_xx = 1,
sections of the transmit hardware are powered down to conserve power.
PWRDNT_xx = 0 on device reset.
Transmit Preemphasis Selection Bit 0, Channel xx. PE0_xx and PE1_xx
select one of three preemphasis settings for the transmit section.
PEO_xx=PE1_xx = 0, Preemphasis is 0%
PEO_xx=1, PE1_xx = 0 or PEO_xx=0, PE1_xx = 1, Preemphasis is
12.5%
PEO_xx=PE1_xx = 1, Preemphasis is 25%.
PEO_xx=PE1_xx = 0 on device reset.
Transmit Half Amplitude Selection Bit, Channel xx. When HAMP_xx = 1,
the transmit output buffer voltage swing is limited to half its normal ampli-
tude. Otherwise, the transmit output buffer maintains its full voltage
swing. HAMP_xx = 0 on device reset.
Reserved. Must be set to 0. Set to 0 on device reset.
Reserved
Transmit 8b/10b Encoder Enable Bit, Channel xx. When 8b10bT_xx = 1,
the 8b/10b encoder in the transmit path is enabled. Otherwise, the data
is passed unencoded. 8b10bT_xx = 0 on device reset.
Receive Half Rate Selection Bit, Channel xx. When RXHR_xx =1,
HDIN_xx's baud rate = (REFCLK[A:B]*10) and RCK78[A:B]=(REF-
CLK[A:B]/4); when RXHR_xx=0, HDIN_xx's baud rate = (REF-
CLK[A:B]*20) and RCK78[A:B]=(REFCLK/2). RXHR_xx = 0 on device
reset.
Receiver Power Down Control Bit, Channel xx. When PWRDNR_xx = 1,
sections of the receive hardware are powered down to conserve power.
PWRDNR_xx = 0 on device reset.
Reserved. Set to 1 on device reset.
Receive 8b/10b Decoder Enable Bit, Channel xx. When 8b10bR = 1, the
8b/10b decoder in the receive path is enabled. Otherwise, the data is
passed undecoded. 8b10bR_xx = 0 on device reset.
Link State Machine Enable Bit, Channel xx. When LINKSM_xx = 1, the
receiver Fiber Channel link state machine is enabled. Otherwise, the
Fibre Channel link state machine is disabled.
Note: LINKSM_xx is ignored when XAUI_MODE_xx=1. LINKSM_xx = 0
on device reset.
Not used.
61
ORCA ORT42G5 and ORT82G5 Data Sheet
Description