H57V2582GTR-60J HYNIX [Hynix Semiconductor], H57V2582GTR-60J Datasheet
H57V2582GTR-60J
Related parts for H57V2582GTR-60J
H57V2582GTR-60J Summary of contents
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Synchronous DRAM based 4Bank x8 I/O 256M (32Mx8bit) Hynix SDRAM - Organized as 4banks of 8,388,608 x 8 This document is a general product description and is subject to change without notice. Hynix does not assume ...
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... Synchronous DRAM Revision History Revision No. 0.1 1.0 Rev 1.0 / Aug. 2009 Synchronous DRAM Memory 256Mbit Document Title History Preliminary Release H57V2582GTR-xxI Series Draft Date Remark Jun. 2009 Aug. 2009 2 ...
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... DESCRIPTION The Hynix H57V2582GTR Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for the con- sumer memory applications which requires large memory density and high bandwidth organized as 4banks of 8,388,608 x 8 I/O. Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK) ...
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... This product is in compliance with the directive pertaining of RoHS. ● ORDERING INFORMATION Clock Part Number Frequency H57V2582GTR-60I 166MHz H57V2582GTR-75I 133MHz H57V2582GTR-60J 166MHz H57V2582GTR-75J 133MHz Note: 1. H57V2582GTR-XXI Series: Normal power & Commercial temp. 2. H57V2582GTR-XXJ Series: Low Power & Commercial temp. Rev 1.0 / Aug. 2009 = 3.3V 3.3V ...
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... BA0 20 BA1 21 A10/ VDD 27 Rev 1.0 / Aug. 2009 Synchronous DRAM Memory 256Mbit 54 Pin TSOPII 400mil x 875mil 0.8mm pin pitch H57V2582GTR-xxI Series VSS 54 DQ7 53 VSSQ DQ6 50 VDDQ DQ5 47 VSSQ DQ4 44 VDDQ VSS ...
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... Multiplexed data input / output pin SUPPLY Power supply for internal circuits and input buffers SUPPLY Power supply for output buffers DDQ SSQ connection : These pads should be left unconnected Rev 1.0 / Aug. 2009 Synchronous DRAM Memory 256Mbit H57V2582GTR-xxI Series DESCRIPTION 6 ...
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... Synchronous DRAM Memory 256Mbit Internal Row Counter 8M x8 Bank3 8M x8 Bank2 Row Pre Decoder Column Pre Decoder Column Add Counter Burst Counter CAS Latency Mode Register H57V2582GTR-xxI Series 8M x8 Bank1 8M x8 Bank0 Memory Cell Array Y decoerders Pipe Line Control Data Out Control DQ0 DQ7 7 ...
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... SS DD DDQ Symbol Min 3.0 DD DDQ Symbol trip outref CL H57V2582GTR-xxI Series Rating - -55 ~ 125 -1.0 ~ 4.6 -1 Max Unit 3 0.3 V DDQ 0.8 V =3.3±0. =0V Value Unit 2 Unit o ...
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... Synchronous DRAM Memory 256Mbit VTT = 1. Ohom Output 50pF AC Output Load Circuit Pin - Symbol Min 2 H57V2582GTR-xxI Series VTT = 1. Ohom Ohom 50pF Symbol Min Max Unit CI1 2.0 4.0 CI2 2.0 4.0 CI3 2.0 4.0 CI/O 3.5 6.5 Max Unit Note 1 uA ...
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... IH CK Input signals are stable. ≥ (min), I =0mA All banks active t ≥ t (min), All banks active RC RC CKE ≤ 0.2V Low Power H57V2562GTR-XXJ Series: Low Power H57V2582GTR-xxI Series Speed Unit 166 133 15ns 15ns ...
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... 1.5 CKS t 0.8 CKH 1.0 OLZ 2.7 OHZ3 OHZ2 & t > 1ns, then [(t +t )/2-1]ns should be added to the parameter H57V2582GTR-xxI Series 133 Unit Max Min Max 1000 7.5 1000 ns 1000 10 1000 5 1.5 - ...
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... WTL t 2 DPL t DAL t 2 DQZ t 0 DQM t 2 MRD PROZ3 PROZ2 t 1 DPE t 1 SRE t - REF after self refresh exit. RC H57V2582GTR-xxI Series 166 133 Unit Max Min Max - 100K 42 100K CLK ...
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... Synchronous DRAM Memory 256Mbit Code 0 0 CAS Latency Burst Length H57V2582GTR-xxI Series Burst Length Burst Type A3 Burst Type 0 Sequential 1 Interleave Burst Length A3 ...
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... Synchronous DRAM Memory 256Mbit H57V2582GTR-xxI Series A10 WE DQM ADDR / Code Row Address Col umn Col umn ...
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... Precharge BA Row Add. Bank Activate Col Add. BA Write/WriteAP A10 Col Add. BA Read/ReadAP A10 Operation H57V2582GTR-xxI Series Action Notes Set the Mode Register Start Auto or Self Refresh 5 No Operation Activate the specified bank and row ILLEGAL 4 ILLEGAL 4 No Operation 3 No Operation or Power ...
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... X Precharge BA Row Add. Bank Activate BA Col Add. A10 Write/WriteAP BA Col Add. A10 Read/ReadAP Operation X X Device Deselect H57V2582GTR-xxI Series Action Notes Continue the Burst ILLEGAL 13 13 Termination Burst: Start 10 the Precharge ILLEGAL 4 Termination Burst: Start 8 Write(optional AP) Termination Burst: Start 8,9 Read(optional AP) ...
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... X X Auto or Self Refresh ILLEGAL BA X Precharge BA Row Add. Bank Activate BA Col Add. A10 Write/WriteAP BA Col Add. A10 Read/ReadAP Operation H57V2582GTR-xxI Series Action Notes ILLEGAL Operation: Bank(s) idle after t RP ILLEGAL 4,12 ILLEGAL 4,12 ILLEGAL 4,12 No Operation: Bank(s) idle after Operation: ...
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... Auto or Self Refresh ILLEGAL BA X Precharge BA Row Add. Bank Activate BA Col Add. A10 Write/WriteAP BA Col Add. A10 Read/ReadAP Operation X X Device Deselect H57V2582GTR-xxI Series Action Notes No Operation: Row Active after t DPL ILLEGAL 13 13 ILLEGAL 4,13 ILLEGAL 4,12 ILLEGAL 4,12 ILLEGAL 4,9,12 No Operation: Precharge after t ...
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... Must mask preceding data which don 11. Illegal not satisfied RRD 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. Rev 1.0 / Aug. 2009 ' t care, BA: Bank Address, AP: Auto Precharge satisfy t . DPL Synchronous DRAM Memory 256Mbit H57V2582GTR-xxI Series 19 ...
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... CODE H57V2582GTR-xxI Series Action ADDR X INVALID Exit Self Refresh with X Device Deselect Exit Self Refresh with X No Operation X ILLEGAL X ILLEGAL X ILLEGAL X Maintain Self Refresh X INVALID X Power Down mode exit, all banks idle ...
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... Command BA0, CS RAS CAS WE BA1 H57V2582GTR-xxI Series Action ADDR Refer to operations of X the Current State Truth Table Begin Clock Suspend X next cycle Exit Clock Suspend X next cycle X Maintain Clock Suspend Notes 21 ...
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... Synchronous DRAM Memory 256Mbit millimeters Typ Max - 1.194 0.100 0.150 1.000 1.050 - 0.400 - 0.210 0.10 22.22 22.327 11.76 11.938 10.16 10.262 0 0.597 0 (min / max) H57V2582GTR-xxI Series α A1 inches Min Typ 0.0390 0.0020 0.0039 0.0374 0.0394 0.012 - 0.0047 - 0.0039 0.8720 0.8748 0.4620 0.4630 0.3950 0.4 - 0.0315 ...