H57V2582GTR-60J HYNIX [Hynix Semiconductor], H57V2582GTR-60J Datasheet - Page 6

• Manufacturer Part Number: H57V2582GTR-60J
• Description: 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev 1.0 / Aug. 2009
54_TSOPII Pin DESCRIPTIONS
RAS, CAS, WE
V
DQ0 ~ DQ7
DDQ
V
SYMBOL
A0 ~ A12
BA0, BA1
DD
DQM
CLK
CKE
NC
CS
/ V
/ V
SS
SSQ
SUPPLY
SUPPLY
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
TYPE
I/O
I/O
-
Clock :
The system clock input. All other inputs are registered to the SDRAM on the rising edge
of CLK
Clock Enable:
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh
Chip Select:
Enables or disables all inputs except CLK, CKE and DQM
Bank Address:
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA9
Auto-precharge flag: A10
Command Inputs:
RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask
Data Input / Output:
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection : These pads should be left unconnected
DESCRIPTION
Synchronous DRAM Memory 256Mbit
H57V2582GTR-xxI Series
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