YMF754-V ETC, YMF754-V Datasheet - Page 22

• Manufacturer Part Number: YMF754-V
• Description: DS-1E
• Manufacturer: ETC

YMF754
4A-4Bh: DS-1E Power Control 1
b2................WRST: AC’97 Warm Reset
b3................ACLS: AC-Link Status
b0................DMC: Disable Master Clock Oscillation
b2................DPLL: Disable PLL Clock Oscillation
b6................JSR: Joystick Reset
b8................PR0: AC’97 Power Down Control 0
PR7
This bit places the AC’97 in warm reset condition when the BIT_CLK signal on the AC’97 remains in
inactive state. If this bit is set to “1”, it will automatically return to “0” after 1.3µs time duration. This
bit is valid only while the ACLS bit is set to “0”. Except in this case, even if this bit is attempted to be
set to “1”, no warm reset will be generated (write operation of “1” remains disabled).
This bit indicates whether or not the AC-link is active. This bit is “1” when the AC-link remains in
active state (the BIT_CLK signal is active).
Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz).
Setting this bit to “1” disables the oscillation of PLL.
This bit controls reset of the flip-flop circuit following the analog comparator stage on the joystick port.
The Initial value is set to “0” immediately after power on reset or hardware reset.
This bit controls the power state of the ADC and Input Mux in the Primary AC’97.
b15
“0”: Normal
“1”: AC’97 Warm Reset
“0”: AC’97 Inactive
“1”: AC’97 Active
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Resets the flip-flop circuit following the analog comparator stage on the joystick port
“0”: Normal
“1”: Power down
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
PR6
b14
PR5
b13
PR4
b12
(default)
(default)
(default)
(default)
(default)
(default)
PR3
b11
PR2
b10
(Read Only)
PR1
b9
-22-
PR0
b8
b7
-
JSR
b6
b5
-
b4
-
b3
-
June 28, 1999
DPLL
b2
b1
-
DMC
b0