YMF754-V ETC, YMF754-V Datasheet - Page 23

• Manufacturer Part Number: YMF754-V
• Description: DS-1E
• Manufacturer: ETC

YMF754
b9................PR1: AC’97 Power Down Control 1
b10..............PR2: AC’97 Power Down Control 2
b11..............PR3: AC’97 Power Down Control 3
b12..............PR4: AC’97 Power Down Control 4
b13..............PR5: AC’97 Power Down Control 5
b14..............PR6: AC’97 Power Down Control 6
b15..............PR7: AC’97 Power Down Control 7
Respective data set to b[15:8] are correspondingly set into the “Power down Ctrl/Stat” register in the Primary
AC’97 via the AC-Link. These are not set into the “Power down Ctrl/Stat” register in the Secondary AC’97.
This bit controls the power state of the DAC in the Primary AC’97.
This bit controls the power state of the Analog Mixer (Vref still on) in the Primary AC’97. This power
state retains the Reference Voltage of the AC’97.
This bit controls the power state of the Analog Mixer (Vref off) in the Primary AC’97. This power
state removes Reference Voltage of the AC’97.
This bit controls the power state of the AC-link in the Primary AC’97.
Setting this bit to “1” disables the internal clock of the Primary AC’97. In case the AC’97 is used with
DS-1E, the master clock is supplied from DS-1E. Therefore, when the clock is stopped completely, set
PR5 bits to “1” firstly, then the CMCD bit should be set to “1” after duration of 1ms or longer.
This bit controls PR6 bit status of the power control register in the Primary AC’97.
This bit controls PR7 bit status of the power control register in the Primary AC’97.
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Disable
(default)
(default)
(default)
(default)
(default)
-23-
June 28, 1999