CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 32

• Manufacturer Part Number: CN8330EPD
• Description: DS3/E3 Framer with 52 Mbps HDLC Controller
• Manufacturer: CONEXANT [Conexant Systems, Inc]

2.0 Functional Description
2.3 Transmitter Operation
Figure 2-6. Transmitter Timing for Serial E3 Mode
2.3.4 Framing Bit Generation
2-10
TDAT[6]/TXDATI
TDAT[7]/TXSYI
TXGAPCK
(Serial In)
VALFCS/
(Sync In)
TXBCK/
TXOVH
TXSYO
TXCKI
In DS3 mode, all F and M framing bits are automatically generated by the
transmitter circuitry. Additionally, the transmitter calculates the parity of each
M-frame and inserts this data into bits P1 and P2 of the following M-frame. Bits
X1 and X2 contain ones unless the Transmit Alarm Control 0 bit [TxAlm0;
CR00.4] in the Mode Control Register [CR00;0x00] is set. If set, bits X1 and X2
contain zeros. If C-bit parity mode is selected, all C-bit positions are generated
automatically by the transmitter if the External C-Bit Insert bit [ExtCBit;CR00.2]
is low. If high, all C-bits are generated internally except for the CP (subframe 3)
an FEBE (subframe 4) bit positions. These bits must be provided on the CBITI
pin at the proper time in response to TXCCK as shown in
data must be valid on the falling edge of TXCCK. This allows the chip to be used
in a repeater mode with pass-through of the path parity and FEBE information. If
C-bit parity mode is not selected, all C-bit positions come from either the serial
data stream or the CBITI pin depending on the ExtCBit setting in the Mode
Control Register. The X, P, M, and F bit positions may be inserted from the
transmit serial data stream by setting External Overhead Insert bit
[ExtOvh;CR00.3] high.
1520/1524 Info Bits
Conexant
10-Bit FAS
Low for 12 Bits (FAS,A,N)
High for 12 Bits (FAS,A,N)
DS3/E3 Framer with 52 Mbps HDLC Controller
A/N/1100
Figure
Info
2-7. The CBITI
CN8330
100441E