CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 41
CN8330EPD
Manufacturer Part Number
CN8330EPD
Description
DS3/E3 Framer with 52 Mbps HDLC Controller
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
1.CN8330EPD.pdf
(101 pages)
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CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure 2-9. Nibble Mode with the PPDLONLY Control Pin Low
100441E
Nibble Data
CK
Register
Q3
Q2
Q1
Q0
•
SMDS applications if desired. To enable nibble-wide transmission, both the
Nibble Mode Enable [Nibble;CR05.0] and DisPPDL bits in the PPDL Control
Register should be set to one. Data should be inserted on the TDAT[3:0] pins;
MSB on TDAT[2], second MSB on TDAT[1], next MSB on TDAT[0], LSB on
TDAT[3] in response to TXBCK/TXGAPCK (which now occurs every 4 bits). In
nibble mode, the nibbles are transmitted MSB first and are nibble-aligned after
each overhead bit in the DS3 frame for a total of 21 nibbles per 85-bit data block.
Nibble mode should not be used for E3 applications. In this mode (Nibble mode
and PPDLONLY pin = 0), the transmit PPDL interface shifts the serial data by
one bit. This anomaly (only on the transmit side) can be remedied by the circuit
shown in
D
CK
D-Type FF
The PPDL transmitter can be used with a nibble-wide interface for DS3
Q
Figure
2-9.
Conexant
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
CN8330
TXBCK
Q Output
Data Bit
2.0 Functional Description
MSB
2SB
1SB
LSB
2.3 Transmitter Operation
TDAT[2]
TDAT[1]
TDAT[0]
D Input
TDAT[3]
Input Pin
2-19
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