CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 59

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CN8330EPD

Manufacturer Part Number
CN8330EPD
Description
DS3/E3 Framer with 52 Mbps HDLC Controller
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
For a summary of all registers, refer to the Register Summary section at the end of this chapter.
3.1 Control Registers
LineLp
SourceLp
TxAlm1,0
100441E
0x00—Mode Control Register (CR00)
LineLp
7
Line Loopback Enable—Set to enable the loopback in the external direction (back to network).
This loopback connects the received data stream before B3ZS/HDB3 decoding to the
transmitter. All data and overhead bits are looped; and Bipolar Violations (BPVs) are fully
preserved per ANSI standard T1.404. The received data is still presented to all receiver blocks
and is present on the receiver output pins.
Source Loopback Enable—Set to enable the loopback in the internal direction. This loopback
connects the encoded transmitter data and clock directly to the receiver B3ZS/HDB3 decoder.
Transmission of data on the line is not affected by this loopback.
Transmit Alarm Control—U sed to control transmission of various alarm signals. In DS3 mode,
the AIS, idle, and yellow alarm signals on the outgoing DS3 stream are controlled as follows:
TxAlm1 bit is set high to transmit the E3 yellow alarm (A-bit high). TxAlm0 bit has
precedence in E3 mode.
SourceLp
In E3 mode, the TxAlm0 bit should be set high to transmit the E3 AIS signal and the
6
TxAlm1
3.0 Registers
3
0
0
1
1
TxAlm1
5
TxAlm0
4
TxAlm0
Conexant
0
1
0
1
ExtOvh
3
Yellow Alarm (X-bits low) Transmitted
Normal, No Alarms Transmitted
ExtCBit
Idle Code Transmitted
2
AIS Transmitted
Alarm Action
E3Frm
1
CBitP/DL
0
3-1

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