CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet - Page 61

• Manufacturer Part Number: CN8330EPD
• Description: DS3/E3 Framer with 52 Mbps HDLC Controller
• Manufacturer: CONEXANT [Conexant Systems, Inc]

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
This Terminal Data Link Control Register controls functions of the terminal data link as defined in C-bit parity
or E3 mode. If C-bit parity or E3 mode is not selected, the contents of this register are ignored.
RxTDLIE
DisTxTDL
TxByte[2:0]
TxAbort
TxFCS
TxMsg
The Status Interrupt Control Register is provided to enable or disable individual interrupt sources. To enable an
interrupt from a particular source, the control bit corresponding to that source must be set high in the interrupt
control register. This enables the interrupt from that source to appear on the CNTINT/LINELB output pin. If a
source has its interrupt control bit set low, then interrupts from this counter will be masked from appearing on
CNTINT/LINELB.
SR6IE
RxFEACIE
LCVCtrIE
FEBECtrIE
PthCtrIE
FerrCtrIE
100441E
0x01—Terminal Data Link Control Register (CR01)
0x02—Status Interrupt Control Register (CR02)
RxTDLIE
SR6IE
7
7
DisTxTDL
Receive Terminal Data Link Interrupt Enable—E nables the Receive Terminal Data Link
Interrupt bit [RxTDLItr;SR02.2] to appear on the DLINT/SOURCELB output pin.
Disable Transmit Terminal Data Link—Forces the output of the Transmit Terminal Data Link
to all ones.
Byte —A 3-bit pointer to the Transmit Terminal Data Link Message Buffer [TxTDL;0x30–0x37]
address containing the last byte to be transmitted.
Abort Message—Causes the data link transmitter to halt the message in progress, send an
abort flag, and then resume transmission of idle flags on the data link.
Send Frame Check Sequence—U sed to control the transmission of the FCS at the end of a
message block.
Send Message—Instructs the transmitter to begin transmission of a message block on the
terminal data link. Setting this bit removes the data link from idle flag transmission mode and
enables interrupts to the controller for data bytes.
RxFEACIE
Shadow Register Interrupt Enable—A control bit that allows interrupts from the Shadow
Status Register [SR06;0x16] to appear on the CNTINT/LINELB output pin.
Receive FEAC Interrupt Enable—A control bit that allows interrupts from the FEAC receiver
to appear on the DLINT/SOURCELB output pin when in C-bit parity mode.
Line Code Violation Counter Interrupt Enable—A control bit that allows interrupts from the
DS3/E3LCV Counter [SR12,SR13;0x25,0x26] to appear on the CNTINT/LINELB output pin.
FEBE Event Counter Interrupt Enable—A control bit that allows interrupts from the DS3
FEBE Event Counter [SR11;0x24] to appear on the CNTINT/LINELB output pin.
Path Parity Error Counter Interrupt Enable—A control bit that allows interrupts from the Path
Parity Error Counter [SR10;0x23] to appear on the CNTINT/LINELB output pin.
Frame Error Counter Interrupt Enable—A control bit that allows interrupts from the Frame
Error Counter [SR09;0x22] to appear on the CNTINT/LINELB output pin.
6
6
TxByte[2]
LCVCtrIE
5
5
FEBECtrIE
TxByte[1]
4
4
Conexant
TxByte[0]
PthCtrIE
3
3
FerrCtrIE
TxAbort
2
2
DgrCtrIE
TxFCS
1
1
3.1 Control Registers
3.0 Registers
ParCtrlE
TxMsg
0
0
3-3