HY5PS1G421LM HYNIX [Hynix Semiconductor], HY5PS1G421LM Datasheet - Page 20

• Manufacturer Part Number: HY5PS1G421LM
• Description: 1Gb DDR2 SDRAM(DDP)
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.2 / Oct. 2005
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the
following timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected
by
MRS addressing mode (ie. sequential or interleave).
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver
impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output
drivers are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.
DQS
CMD
CK
CK
DQS
DQ
CMD
DQS_in
DQ_in
CK
DM
CK
1
OCD adjust mode
Enter Drive mode
Hi-Z
Other Combinations
EMRS
EMRS
0
tOIT
WL
1
NOP
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0)
NOP
0
tDS
NOP
D
Decrease by 1 step
T0
tDH
D
T1
DQS
NOP
NOP
D
DQs high for Drive(1)
DQs low for Drive(0)
T2
D
T3
NOP
Reserved
NOP
Decrease by 1 step
NOP
OCD calibration mode exit
OCD calibration mode exit
WR
1HY5PS12421(L)M
HY5PS12821(L)M
EMRS
EMRS
tOIT
NOP
Hi-Z
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