HY5PS1G421LM HYNIX [Hynix Semiconductor], HY5PS1G421LM Datasheet - Page 27

• Manufacturer Part Number: HY5PS1G421LM
• Description: 1Gb DDR2 SDRAM(DDP)
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.2 / Oct. 2005
2.5.1 Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2
SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the
RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD, period). The command is held for the
time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of
AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater
than 0) must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (read latency -1) where
read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL
allow seamless bursts (refer to semaless operation timing diagram examples in Read burst and Wirte burst section)
Examples of posted CAS operation
Example 1
Example 2
[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4]
CK/CK
CK/CK
CMD
DQS/DQS
CMD
DQS/DQS
DQ
DQ
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4]
Read followed by a write to the same bank
Read followed by a write to the same bank
-1
-1
A-Bank
A-Bank
Active
Active
0
0
A-Bank
Read
> = tRCD
> = tRCD
1
1
AL = 2
2
2
> = tRAC
> = tRAC
AL = 0
A-Bank
Read
3
3
RL = AL + CL = 5
RL = AL + CL = 3
4
4
CL = 3
CL = 3
A-Bank
Write
5
5
6
6
Dout0
Dout0
WL = RL -1 = 4
Dout1
Dout1
A-Bank
Write
7
7
Dout2
Dout2
WL = RL -1 = 2
Dout3
Dout3
8
8
9
Din0
9
Din0
1HY5PS12421(L)M
HY5PS12821(L)M
Din1
Din1
10
10
Din2
Din2
Din3
Din3
11
11
12
12
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