HY5PS1G421LM HYNIX [Hynix Semiconductor], HY5PS1G421LM Datasheet - Page 72

• Manufacturer Part Number: HY5PS1G421LM
• Description: 1Gb DDR2 SDRAM(DDP)
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.2 / Oct. 2005
7. AC Timing Specifications
7.1 Timing Parameters by Speed Grade
DQ output access time from
CK/CK
DQS output access time from
CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse
width for each input
DQ and DM input pulse width for
each input
Data-out high-impedance time
from CK/CK
DQS low-impedance time from
CK/CK
DQ low-impedance time from
CK/CK
DQS-DQ skew for DQS and
associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from
DQS
Write command to first DQS
latching transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from
CK
Mode register set command cycle
time
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH
tDS
tIPW
tDIPW
tHZ
tLZ
(DQS)
tLZ
(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
Symbol
tHP - tQHS
WL - 0.25
2*tAC min
min(tCL,
tAC min
5000
tCH)
-600
-500
0.45
0.45
0.35
0.35
0.35
min
400
400
0.6
0.2
0.2
DDR2-400 3-3-3
2
-
-
-
WL + 0.25
tAC max
tAC max
tAC max
+600
+500
max
0.55
0.55
8000
350
450
-
-
-
-
-
-
-
-
-
-
-
tHP - tQHS
WL - 0.25
2*tAC min
min(tCL,
tAC min
3750
0.45
0.45
tCH)
0.35
0.35
min
-500
-450
350
350
0.35
0.6
0.2
0.2
DDR2-533 4-4-4
2
-
-
-
1HY5PS12421(L)M
HY5PS12821(L)M
WL + 0.25
tAC max
tAC max
tAC max
+500
+450
8000
max
0.55
0.55
300
400
-
-
-
-
-
-
-
-
-
-
-
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
11,12
Note
6,7,8
6,7,8
15
13
12
72