EN29F040A EON [Eon Silicon Solution Inc.], EN29F040A Datasheet - Page 8

• Manufacturer Part Number: EN29F040A
• Description: 4 Megabit (512K x 8-bit) Flash Memory
• Manufacturer: EON [Eon Silicon Solution Inc.]

Table 5. EN29F040A Command Definitions
Notes:
RA = Read Address: address of the memory location to be read.
RD = Read Data: data read from location RA during Read operation.
PA = Program Address: address of the memory location to be programmed
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the Sector to be erased. Address bits A18-A16 uniquely select any Sector.
The data is 00h for an unprotected sector and 01h for a protected sector.
Byte Programming Command
Programming the EN29F040A is performed on a byte-by-byte basis using a four bus-cycle operation
(two unlock write cycles followed by the Program Setup command and Program Data Write cycle).
When the program command is executed, no additional CPU controls or timings are necessary. An
internal timer terminates the program operation automatically. Address is latched on the falling edge
of CE or
The program operation is completed when EN29F040A returns the equivalent data to the
programmed location.
Programming status may be checked by sampling data on DQ7 ( DATA polling) or on DQ6 (toggle
bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is
exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read
mode.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
chip erase command, which in turn invokes the Embedded Erase algorithm. The device does
the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations. The Command Definitions table shows the
address and data requirements for the chip erase command sequence.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Sector Erase Suspend
Sector Erase Resume
AutoSelect Device ID
AutoSelect Sector
Read/Reset
Manufacturer ID
Command
Sequence
Byte Program
Protect Verify
Sector Erase
Read/Reset
Chip Erase
AutoSelect
Reset
Read
W E
, whichever is last; data is latched on the rising edge of CE or
Cycles
Req’d
Write
1
1
4
4
4
4
4
6
6
1
1
Addr
XXXh
555h
555h
555h
555h
555h
555h
555h
xxxh
xxxh
Write Cycle
RA
1
st
Data
AAh
AAh
AAh
AAh
AAh
AAh
AAh
F0h
B0h
30h
RD
Addr
2AAh
2AAh
2AAh
2AAh
2AAh
2AAh
2AAh
Write Cycle
Rev. B, Issue Date: 2004/04/01
2
nd
8
Data
55h
55h
55h
55h
55h
55h
55h
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Addr
555h
555h
555h
555h
555h
555h
555h
Write Cycle
This one is a read cycle.
3
This one is a read cycle.
rd
Data
F0h
A0h
90h
90h
90h
80h
80h
Addr
000h/
001h/
100h
101h
BA &
555h
555h
Write Cycle
02h
RA
PA
4
th
Data
7Fh/
7Fh/
00h/
AAh 2AAh 55h
AAh 2AAh 55h
1Ch
04h
01h
W E
RD
PD
EN29F040A
, whichever is first.
Addr
Write Cycle
5
th
not
Data
require
Addr
555h
Write Cycle
SA
6
th
Data
10h
30h