EN29LV400AB-70TCP Eon Silicon Solution Inc., EN29LV400AB-70TCP Datasheet
EN29LV400AB-70TCP
Available stocks
Related parts for EN29LV400AB-70TCP
EN29LV400AB-70TCP Summary of contents
Page 1
EN29LV400A 4 Megabit (512K x 8-bit / 256K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only FEATURES • 3V, single power supply operation - Full voltage range: 2.7-3.6 volt read and write operations for battery-powered applications. - ...
Page 2
CONNECTION DIAGRAMS A15 1 A14 2 A13 3 A12 4 A11 5 A10 WE# 11 RESET RY/BY A17 ...
Page 3
TABLE 1. PIN DESCRIPTION Pin Name Function A0-A17 Addresses DQ0-DQ14 15 Data Inputs/Outputs DQ15 (data input/output, word mode), DQ15 / A-1 A-1 (LSB address input, byte mode) CE# Chip Enable OE# Output Enable RESET# Hardware Reset Pin RY/BY# Ready/Busy Output ...
Page 4
TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTURE ADDRESS RANGE Sector (X16) 10 3E000h-3FFFFh 9 3D000h-3DFFFh 8 3C000h-3CFFFh 7 38000h-3BFFFh 6 30000h-37FFFh 5 28000h-2FFFFh 4 20000h-27FFFh 3 18000h-1FFFFh 2 10000h-17FFFh 1 08000h-0FFFFh 0 00000h-07FFFh This Data Sheet may be revised by ...
Page 5
TABLE 2B. BOTTOM BOOT BLOCK SECTOR ARCHITECTURE ADDRESS RANGE Sector (X16) 10 38000h-3FFFFh 9 30000h-37FFFh 8 28000h-2FFFFh 7 20000h-27FFFh 6 18000h-1FFFFh 5 10000h-17FFFh 4 08000h-0FFFFh 3 04000h-07FFFh 2 03000h-03FFFh 1 02000h-02FFFh 0 00000h-01FFFh This Data Sheet may be revised by ...
Page 6
PRODUCT SELECTOR GUIDE Product Number Regulated Voltage Range: Vcc=3.0-3.6 V Speed Option Full Voltage Range: Vcc=2.7 – 3.6 V Max Access Time acc Max CE# Access Max OE# Access ...
Page 7
TABLE 3. OPERATING MODES Operation CE# Read L Write L ± 0.3V CMOS Standby V cc TTL Standby H Output Disable L Hardware Reset X Temporary Sector Unprotect X Notes: L=logic low H=Logic High ...
Page 8
USER MODE DEFINITIONS Word / Byte Configuration The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the ...
Page 9
To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V . See “Command Definitions” for details on using the ...
Page 10
Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t independent of the CE#, WE# and OE# control signals. Standard address access timings provide new data ...
Page 11
COMMAND DEFINITIONS The operations of the EN29LV400A are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are ...
Page 12
Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t-care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing ...
Page 13
The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data ...
Page 14
The system must write the Erase Resume command (address bits are don’t-care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after ...
Page 15
DQ6: Toggle Bit I The EN29LV400A provides a “Toggle Bit” on DQ6 to indicate the status of the embedded programming and erase operations. (See Table 6) During an embedded Program or Erase operation, successive attempts to read data from the ...
Page 16
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. ...
Page 17
Table 6. Status Register Bits DQ Name DATA# 7 POLLING TOGGLE 6 BIT 5 ERROR BIT ERASE 3 TIME BIT TOGGLE 2 BIT Notes: DQ7 DATA# Polling: indicates the P/E C status check during Program or Erase, and on completion ...
Page 18
EMBEDDED ALGORITHMS Flowchart 1. Embedded Program Increment No Address Flowchart 2. Embedded Program Command Sequence See the Command Definitions section for more information on WORD mode. 555H / AAH 2AAH / 55H 555H / A0H PROGRAM ADDRESS / PROGRAM DATA ...
Page 19
Flowchart 3. Embedded Erase START Write Erase Command Sequence Data Poll from System or Toggle Bit successfully completed Data =FFh? No Erase Done Flowchart 4. Embedded Erase Command Sequence See the Command Definitions section for more information on WORD mode. ...
Page 20
Flowchart 5. DATA# Polling Algorithm Notes: (1) This second read is necessary in case the first read was done at the exact instant when the status data was in transition. Flowchart 6. Toggle Bit Algorithm Notes: (2) This second set ...
Page 21
Flowchart 7a. In-System Sector Protect Flowchart Temporary Sector Unprotect Mode Increment PLSCNT PLSCNT = 25? Device failed Sector Protect Algorithm This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. START PLSCNT = ...
Page 22
Flowchart 7b. In-System Sector Unprotect Flowchart Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see Diagram 7a.) Increment PLSCNT No PLSCCNT = ...
Page 23
Table 7. DC Characteristics (T = 0°C to 70° 40°C to 85° Symbol Parameter Input Leakage Current I LI Output Leakage Current I LO Supply Current (read) TTL (read) CMOS Byte I CC1 (read) CMOS ...
Page 24
Test Conditions Device Under Test C L Note: Diodes are IN3064 or equivalent Test Specifications Test Conditions Output Load Output Load Capacitance, C Input Rise and Fall times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference ...
Page 25
AC CHARACTERISTICS Hardware Reset (Reset#) Parameter Description Std Reset# Pin Low to Read or Write t READY Embedded Algorithms Reset# Pin Low to Read or Write t READY Non Embedded Algorithms t Reset# Pulse Width RP t Reset# High Time ...
Page 26
AC CHARACTERISTICS Word / Byte Configuration (Byte#) Std Parameter Description t Byte# to CE# switching setup time BCS t CE# to Byte# switching hold time CBH t RY/BY# to Byte# switching hold time RBH CE# OE# Byte# CE# WE# Byte# ...
Page 27
Table 8. AC CHARACTERISTICS Read-only Operations Characteristics Parameter Symbols Description JEDEC Standard t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable To Output Delay ELQV Output Enable ...
Page 28
Table 9. AC CHARACTERISTICS Write (Erase/Program) Operations Parameter Symbols JEDEC Standard Description t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH DS ...
Page 29
Table 10. AC CHARACTERISTICS Write (Erase/Program) Operations Alternate CE# Controlled Writes Parameter Symbols Description JEDEC Standard t t Write Cycle Time AVAV Address Setup Time AVEL Address Hold Time ELAX Data ...
Page 30
Table 11. ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Byte Chip Programming Time Word Erase/Program Endurance Table 12. LATCH UP CHARACTERISTICS Parameter Description Input voltage with respect ...
Page 31
AC CHARACTERISTICS Figure 6. AC Waveforms for Chip/Sector Erase Operations Timings Erase Command Sequence (last 2 cycles Addresses 0x2AA CE# t GHWL OE WE Data 0x55 t DS RY/BY VCS ...
Page 32
Figure 7. Program Operation Timings Program Command Sequence (last 2 cycles Addresses 0x555 CE# t GHWL OE WE Data OxA0 t DS RY/BY# t VCS V CC Notes: 1. PA=Program Address, PD=Program ...
Page 33
Figure 8. AC Waveforms for DATA# Polling During Embedded Algorithm Operations t RC Addresses VA t ACC CE OE# t OEH WE# DQ[7] DQ[6:0] t BUSY RY/BY# Notes: 1. VA=Valid Address for reading Data# ...
Page 34
Figure 10. Alternate CE# Controlled Write Operation Timings 0x555 for Program 0x2AA for Erase Addresses t WC WE# t GHEL OE CE Data 0xA0 for Program RY/BY Reset# Notes address ...
Page 35
Figure 12. Sector Protect/Unprotect Timing Diagram V ID Vcc RESET VIDR SA, A6,A1,A0 Data 60h Sector Protect/Unprotect CE# WE# >1μS OE# Notes: Use standard microprocessor timings for this device for read and write cycles. For Sector Protect, use ...
Page 36
FIGURE 14. 48L TSOP 12mm x 20mm package outline This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. ©2005 Eon Silicon Solution, Inc., www.essi.com.tw 36 Rev. D, Issue Date: 2008/04/25 EN29LV400A ...
Page 37
FIGURE 15. 48L TFBGA 6mm x 8mm package outline This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. SYMBOL Note : 1. Coplanarity: ...
Page 38
ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Plastic Packages Ambient Temperature With Power Applied Output Short Circuit Current A9, OE#, Reset# Voltage with Respect to Ground Notes more than one output shorted at a time. Duration of the short ...
Page 39
... Regulated range 3.0V~3. 70ns 90 = 90ns BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector BASE PART NUMBER EN = Eon Silicon Solution Inc. 29LV = FLASH, 3V Read Program Erase 400 = 4 Megabit (512K 256K x 16 Version Identifier ©2005 Eon Silicon Solution, Inc., www.essi.com.tw 39 Rev. D, Issue Date: 2008/04/25 ...
Page 40
Revisions List Revision No Description A Initial Release B 1. Correct the typo of program/erase Endurance cycle to 100K at FEATURES page 1 2. Change the FBGA package dimension to enhance the BGA substrate and ball strength, the difference is ...