EN29LV400AB45RBCP EON [Eon Silicon Solution Inc.], EN29LV400AB45RBCP Datasheet
EN29LV400AB45RBCP
Related parts for EN29LV400AB45RBCP
EN29LV400AB45RBCP Summary of contents
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Purpose Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the ICs. ...
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EN29LV400A 4 Megabit (512K x 8-bit / 256K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only FEATURES • 3V, single power supply operation - Full voltage range: 2.7-3.6 volt read and write operations for battery-powered applications. - ...
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CONNECTION DIAGRAMS A15 1 A14 2 A13 3 A12 4 A11 5 A10 WE# 11 RESET RY/BY A17 ...
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DQ8 DQ10 CE OE# DQ9 DQ0 DQ1 This Data Sheet may be ...
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TABLE 1. PIN DESCRIPTION Pin Name Function A0-A17 Addresses DQ0-DQ14 15 Data Inputs/Outputs DQ15 (data input/output, word mode), DQ15 / A-1 A-1 (LSB address input, byte mode) CE# Chip Enable OE# Output Enable RESET# Hardware Reset Pin RY/BY# Ready/Busy Output ...
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TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTURE ADDRESS RANGE Sector (X16) 10 3E000h-3FFFFh 9 3D000h-3DFFFh 8 3C000h-3CFFFh 7 38000h-3BFFFh 6 30000h-37FFFh 5 28000h-2FFFFh 4 20000h-27FFFh 3 18000h-1FFFFh 2 10000h-17FFFh 1 08000h-0FFFFh 0 00000h-07FFFh This Data Sheet may be revised by ...
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TABLE 2B. BOTTOM BOOT BLOCK SECTOR ARCHITECTURE ADDRESS RANGE Sector (X16) 10 38000h-3FFFFh 9 30000h-37FFFh 8 28000h-2FFFFh 7 20000h-27FFFh 6 18000h-1FFFFh 5 10000h-17FFFh 4 08000h-0FFFFh 3 04000h-07FFFh 2 03000h-03FFFh 1 02000h-02FFFh 0 00000h-01FFFh This Data Sheet may be revised by ...
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PRODUCT SELECTOR GUIDE Product Number Regulated Voltage Range: Vcc=3.0-3.6 V Speed Option Full Voltage Range: Vcc=2.7 – 3.6 V Max Access Time acc Max CE# Access Max OE# Access ...
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TABLE 3. OPERATING MODES Operation CE# Read L Write L ± 0.3V CMOS Standby V cc Output Disable L Hardware Reset X Temporary Sector X Unprotect Notes: L=logic low H=Logic High =Data ...
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USER MODE DEFINITIONS Word / Byte Configuration The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the ...
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Write Mode Write operations, including programming data and erasing sectors of memory, require the host system to write a command or command sequence to the device. Write cycles are initiated by placing the byte or word address on the device’s ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which ...
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COMMAND DEFINITIONS The operations of the EN29LV400A are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are ...
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Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t- care for this command. The reset command may be written between the sequence cycles in an erase command sequence before ...
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The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data ...
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WRITE OPERATION STATUS DQ7: DATA# Polling The EN29LV400A provides DATA# polling on DQ7 to indicate the status of the embedded operations. The DATA# polling feature is active during the embedded Programming, Sector Erase, Chip Erase, and Erase Suspend. (See Table ...
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In embedded Programming, if the sector being written to is protected, DQ6 will toggles for about 2 μs, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are ...
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However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5 is, the system ...
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Table 6. Status Register Bits DQ Name DATA# 7 POLLING 6 TOGGLE BIT 5 TIME OUT BIT ERASE TIME 3 OUT BIT 2 TOGGLE BIT Notes: DQ7 DATA# Polling: indicates the P/E C status check during Program or Erase, and ...
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EMBEDDED ALGORITHMS Flowchart 1. Embedded Program Command Sequence No Increment Address Flowchart 2. Embedded Program Command Sequence See the Command Definitions section for more information on WORD mode. 555H / AAH 2AAH / 55H 555H / A0H PROGRAM ADDRESS / ...
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Flowchart 3. Embedded Erase START Write Erase Command Sequence Data Poll from System or Toggle Bit successfully completed Data =FFh? No Erase Done Flowchart 4. Embedded Erase Command Sequence See the Command Definitions section for more information on WORD mode. ...
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Flowchart 5. DATA# Polling Algorithm Notes: (1) This second read is necessary in case the first read was done at the exact instant when the status data was in transition. Flowchart 6. Toggle Bit Algorithm Notes: (2) This second set ...
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Flowchart 7a. In-System Sector Protect Flowchart Temporary Sector Unprotect Mode Increment PLSCNT PLSCNT = 25? Device failed Sector Protect Algorithm This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. START PLSCNT = ...
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Flowchart 7b. In-System Sector Unprotect Flowchart Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see Diagram 7a.) Increment PLSCNT No PLSCCNT = ...
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Table 7. DC Characteristics (T = 0°C to 70° 40°C to 85° Symbol Parameter Input Leakage Current I LI Output Leakage Current I LO Supply Current (read) CMOS Byte I CC1 (read) CMOS Word Supply ...
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Test Conditions Device Under Test Test Specifications Test Conditions Output Load Capacitance, C Input Rise and Fall times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels This Data Sheet may be revised by subsequent versions ...
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AC CHARACTERISTICS Hardware Reset (Reset#) Parameter Std RESET# Pulse Width (During Embedded t RP1 Algorithms) RESET# Pulse Width (NOT During Embedded t RP2 Algorithms) t Reset# High Time Before Read RH t RY/BY# Recovery Time ( to CE#, OE# go ...
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AC CHARACTERISTICS Word / Byte Configuration (Byte#) Std Description Parameter t Byte# to CE# switching setup time BCS t CE# to Byte# switching hold time CBH t RY/BY# to Byte# switching hold time RBH Figure 2. AC Waveforms for BYTE# ...
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Table 8. AC CHARACTERISTICS Read-only Operations Characteristics Parameter Symbols JEDEC Standard Description t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable To Output Delay ELQV Output Enable ...
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Table 9. AC CHARACTERISTICS Write (Erase/Program) Operations Parameter Symbols JEDEC Standard Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time ...
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Table 10. AC CHARACTERISTICS Write (Erase/Program) Operations Alternate CE# Controlled Writes Parameter Symbols JEDEC Standard Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX AH t ...
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Table 11. ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Byte Chip Programming Time Word Erase/Program Endurance Table 12. 48-PIN TSOP AND BGA PACKAGE CAPACITANCE Parameter Symbol Parameter Description C Input ...
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AC CHARACTERISTICS Figure 4. AC Waveforms for Chip/Sector Erase Operations Timings Erase Command Sequence (last 2 cycles Addresses 0x2AA CE# t GHW Data 0x55 t DS RY/BY VCS ...
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Figure 5. Program Operation Timings Program Command Sequence (last 2 cycles Addresses 0x555 CE# t GHWL OE WE Data OxA0 t DS RY/BY# t VCS V CC Notes: 1. PA=Program Address, PD=Program ...
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Figure 6. AC Waveforms for DATA# Polling During Embedded Algorithm Operations t RC Addresses ACC CE OE# t OEH WE# DQ[7] DQ[6:0] t BUSY RY/BY# Notes: 1. VA=Valid Address for reading Data# ...
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Figure 8. Alternate CE# Controlled Write Operation Timings 0x555 for Program 0x2AA for Erase Addresses t WC WE# t GHEL OE CE Data 0xA0 for Program 0x55 for Erase RY/ ...
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Figure 10. Sector Protect/Unprotect Timing Diagram V ID Vcc RESET VIDR SA, A6,A1,A0 Data 60h Sector Protect/Unprotect CE# WE# >1μS OE# Notes: Use standard microprocessor timings for this device for read and write cycles. For Sector Protect, use ...
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FIGURE 12. 48L TSOP 12mm x 20mm package outline This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 38 © 2005 Eon Silicon Solution, Inc., Rev. H, Issue Date: 2011/10/27 EN29LV400A www.eonssi.com ...
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FIGURE 13. 48L TFBGA 6mm x 8mm package outline This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. SYMBOL Note : 1. Coplanarity: ...
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Figure 14. 48L WFBGA 4mm x 6mm package outline Note : Controlling dimensions are in millimeters (mm). This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. © 2005 Eon Silicon Solution, Inc., ...
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ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Plastic Packages Ambient Temperature With Power Applied Output Short Circuit Current A9, OE#, Reset# Voltage with Respect to Ground Notes more than one output shorted at a time. Duration of the short ...
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ORDERING INFORMATION ─ EN29LV400A T 70 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications PACKAGING CONTENT P = RoHS compliant TEMPERATURE RANGE C = Commercial (0°C to +70°C) ...
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Revisions List Revision No Description A Initial Release 1. Correct the typo of program/erase Endurance cycle to 100K at FEATURES page 1 2. Change the FBGA package dimension to enhance the BGA B substrate and ball strength, the difference is ...