TDK5110FHTMA1 Infineon, TDK5110FHTMA1 Datasheet - Page 29

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TDK5110FHTMA1

Manufacturer Part Number
TDK5110FHTMA1
Description
Transmitter Ask/Fsk Sgl Tssop10
Manufacturer
Infineon
Datasheet
Wireless Components
4.6 Design hints on the buffered clock output (CLKOUT)
If the FSK switch is closed, Cv_ is equal to Cv1 (C6 in the application diagram).
If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated.
Csw:
Remark:
The 434 MHz
The 868 MHz
The CLKOUT pin is an open collector output. An external pull up resistor (RL)
should be connected between this pin and the positive supply voltage. The
value of RL is depending on the clock frequency and the load capacitance CLD
(PCB board plus input capacitance of the microcontroller). RL can be calculated
to:
Remark: To achieve a low current consumption and a low
Table 4-2
CL pF
5
10
20
parallel capacitance of the FSK switch (3 pF incl. layout parasitics)
spurious radiation, the largest possible RL should be chosen.
These calculations are only approximations. The necessary values
depend on the layout also and must be adapted for the specific
application board.
50 -Output testboard shows an FSK-deviation of +/- 24 kHz, typically.
50 -Output testboard shows an FSK-deviation of +/- 27 kHz, typically.
fCLKOUT=
Cv
847 kHz
2
C
4 - 9
RL
7
RL k
6.8
27
12
Csw
fCLKOUT
Cv
1
(
Cv
1
(
*
Cv
8
)
*
CL pF
CLD
)
10
20
Cv
5
(
Cv
1
Specification, October 2002
1
fCLKOUT=
3.39 MHz
Csw
)
Applications
RL k
TDK 5110
6.8
3.3
1.8

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