FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet

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FM33256B-G

Manufacturer Part Number
FM33256B-G
Description
Real Time Clock 256Kb F-RAM Processor Companion
Manufacturer
Cypress Semiconductor
Datasheet

Specifications of FM33256B-G

Rohs
yes
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
SOIC-14
Factory Pack Quantity
56

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FM33256B
3V Integrated Processor Companion with F-RAM
Features
High Integration Device Replaces Multiple Parts
Ferroelectric Nonvolatile RAM
Real-time Clock/Calendar
Description
The FM33256B device integrates F-RAM memory
with the most commonly needed functions for
processor-based systems. Major features include
nonvolatile memory, real-time clock, low-V
watchdog timer, nonvolatile event counter, lockable
64-bit serial number area, and general purpose
comparator that can be used for a power-fail (NMI)
interrupt or other purpose. The device operate from
2.7 to 3.6V.
The FM33256B provides 256Kb memory capacity of
nonvolatile F-RAM. Fast write speed and unlimited
endurance allow the memory to serve as extra RAM
or conventional nonvolatile storage. This memory is
truly nonvolatile rather than battery backed.
The real-time clock (RTC) provides time and date
information in BCD format. It can be permanently
powered from external backup voltage source, either
a battery or a capacitor. The timekeeper uses a
common external 32.768 kHz crystal and provides a
calibration mode that allows software adjustment of
timekeeping accuracy.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
Serial Nonvolatile Memory
Real-time Clock (RTC) with Alarm
Low V
Watchdog Window Timer
Early Power-Fail Warning/NMI
16-bit Nonvolatile Event Counter
Serial Number with Write-lock for Security
256Kb F-RAM
High Endurance 100 Trillion (10
38 year Data Retention (+75°C)
NoDelay™ Writes
Backup Current at 2V, 1.15 µA (max.) at +25C
Seconds through Centuries in BCD format
Tracks Leap Years through 2099
Uses Standard 32.768 kHz Crystal
Software Calibration
Supports Battery or Capacitor Backup
DD
Detection Drives Reset
14
) Read/Writes
DD
reset,
Processor Companion
Fast SPI Interface
Easy to Use Configuration
The processor companion includes commonly needed
CPU support functions. Supervisory functions
include a reset output signal controlled by either a
low V
active when V
threshold and remains active for 100 ms (max.) after
V
watchdog timer runs from 60 ms to 1.8 seconds. The
timer may also be programmed for a delayed start,
which functions as a window timer. The watchdog
timer is optional, but if enabled it will assert the reset
signal for 100 ms if not restarted by the host within
the time window. A flag-bit indicates the source of
the reset.
A comparator on PFI compares an external input pin
to the onboard 1.5V reference. This is useful for
generating a power-fail interrupt (NMI) but can be
used for any purpose. The family also includes a
programmable 64-bit serial number that can be
locked making it unalterable. Additionally it offers an
event counter that tracks the number of rising or
falling edges detected on a dedicated input pin. The
counter can be programmed to be non-volatile under
V
V
events will be counted even in the absence of V
DD
DD
BAK
Active-low Reset Output for V
Comparator for Power-Fail Interrupt or Other Use
64-bit Programmable Serial Number with Lock
Up to 16 MHz Maximum Bus Frequency
RTC, Supervisor Controlled via SPI Interface
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Operates from 2.7 to 3.6V
Small Footprint “Green” 14-pin SOIC (-G)
Low Operating Current
-40°C to +85°C Operation
Underwriters Laboratory (UL) Recognized
Programmable Low-V
Manual Reset Filtered and Debounced
Programmable Watchdog Window Timer
Nonvolatile Event Counter Tracks System
Intrusions or other Events
power or battery-backed using only V
rises above the trip point. A programmable
DD
is connected to a battery or capacitor, then
condition or a watchdog timeout. /RST goes
1850 Ramtron Drive, Colorado Springs, CO 80921
DD
Ramtron International Corporation
drops below a programmable
(800) 545-FRAM, (719) 481-7000
DD
Reset Thresholds
DD
www.ramtron.com
and Watchdog
Page 1 of 28
BAK
DD
.
. If

Related parts for FM33256B-G

FM33256B-G Summary of contents

Page 1

... The device operate from 2.7 to 3.6V. The FM33256B provides 256Kb memory capacity of nonvolatile F-RAM. Fast write speed and unlimited endurance allow the memory to serve as extra RAM or conventional nonvolatile storage. This memory is truly nonvolatile rather than battery backed ...

Page 2

... VSS Supply Ground This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Rev. 3.0 Aug. 2012 FM33256B SPI Companion w/ FRAM Pin Name /CS VDD SCK SI ACS SO SCK ...

Page 3

... Max. Clock Reset Thresholds Freq. 16 MHz 2.6V, 2.75, 2.9, 3.0V 16 MHz 2.6V, 2.75, 2.9, 3.0V FM33256B SPI Companion w/ FRAM FRAM Array RTC Registers X1 RTC X2 Alarm Alarm ACS 512Hz/SqW Ordering Part Number FM33256B-G FM33256B-GTR (tape&reel) Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com Page ...

Page 4

... Supervisors provide a host processor two basic functions: Detection of power supply fault conditions and a watchdog timer to escape a software lockup condition. The FM33256B has a reset pin (/RST) to drive a processor reset input during power faults, power-up, and software lockups open drain output with a weak internal pull- allows other reset sources to be wire-OR’ ...

Page 5

... Manual Reset The /RST is a bi-directional signal allowing the FM33256B to filter and de-bounce a manual reset switch. The /RST input detects an external low condition and responds by driving the /RST signal low for 100 ms (max.). This effectively filters and de- bounces a reset switch ...

Page 6

... V PFO output will drive to V reset is DD Event Counter The FM33256B offers the user a nonvolatile 16-bit event counter. programmable edge detector. The CNT pin clocks the counter. The counter is located in registers 0E-0Fh. When the programmed edge polarity occurs, the counter will increment its count value ...

Page 7

... CNT pin and the other contact to the case chassis, usually ground. The typical solution uses a pullup resistor on the CNT pin and will continuously draw battery current. The FM33256B chip allows the user to invoke a polled mode, which occasionally samples the pin in order to minimize battery drain. It ...

Page 8

... The product has completed Ramtron’s internal qualification testing and has reached production status. Rev. 3.0 Aug. 2012 FM33256B SPI Companion w/ FRAM The ACS output may also be used to drive the system with a frequency other than 512 Hz. The AL/SW bit (register 18h, bit 6) must be ‘0’. A user-selectable frequency is provided by F0 and F1 (register 18h, bits 4 and 5) ...

Page 9

... BAK . The BAK The minimum V temperature. The user can expect the minimum V voltage to be 1.23V at +85°C and 1.90V at -40°C. The tested limit is 1.55V at +25°C. Figure 11. V FM33256B SPI Companion w/ FRAM 512 out Update Logic 1 Hz Minutes ...

Page 10

... The FM33256B device has built-in loading capacitors that match the crystal. BAK If a 32.768kHz crystal is not used, an external oscillator may be connected to the FM33256B. Refer to Application Note AN407 for recommendations on Ω series how to implement this. ...

Page 11

... This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Rev. 3.0 Aug. 2012 FM33256B SPI Companion w/ FRAM Layout for Through Hole Crystal (red = top layer, green = bottom layer) Error Range (PPM) Min ...

Page 12

... This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Rev. 3.0 Aug. 2012 FM33256B SPI Companion w/ FRAM Error Range (PPM) Min Max Program Calibration Register to ...

Page 13

... FM33256B SPI Companion w/ FRAM D1 D0 Function Alarm Month Alarm Date Alarm Hours Alarm Minutes Alarm Seconds VTP0 Companion Control Serial Number 7 Serial Number 6 Serial Number 5 Serial Number 4 ...

Page 14

... Hours min.1 10 min.0 Min sec.1 10 sec.0 Seconds VBC F(1:0) Setting 00 (default) 4096 Hz 01 32768 Hz DD FM33256B SPI Companion w/ FRAM Month.2 Month.1 Month Date.2 Date.1 Date Hours2 Hours.1 Hours Min.2 Min.1 Min Seconds ...

Page 15

... If the NVC bit is changed, the counter value is not valid. Nonvolatile, read/write. BAK DD This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Rev. 3.0 Aug. 2012 FM33256B SPI Companion w/ FRAM SN.61 SN.60 SN.59 D5 ...

Page 16

... Ramtron Drive, Colorado Springs, CO 80921 FM33256B SPI Companion w/ FRAM WDET2 WDET1 WDET0 ...

Page 17

... RTC/alarm when year.1 10 year.0 Year Month Month date.1 10 date.0 Date FM33256B SPI Companion w/ FRAM WR2 WR1 WR0 Year.2 Year.1 Year Month.2 Month.1 Month ...

Page 18

... Hours min.1 10 min.0 Min sec.1 10 sec.0 Seconds CALS CAL.4 CAL AEN Reserved FM33256B SPI Companion w/ FRAM Hours2 Hours.1 Hours Min.2 Min.1 Min Seconds.2 Seconds.1 Seconds CAL.2 CAL.1 CAL CAL ...

Page 19

... For both modes, data is clocked into the to FM33256B on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge ...

Page 20

... SCK. Outputs are driven from the falling edge of SCK. Command Structure There are eight commands called op-codes that can be issued by the bus master to the FM33256B. They are listed in the table below. These op-codes control the functions performed by the memory and Processor Companion. They can be divided into three categories ...

Page 21

... Status Register. Reading this register provides information about the current state of the write protection bits. Following the RDSR op- code, the FM33256B will return one byte with the contents of the Status Register. The Status Register is described in detail in a later section. ...

Page 22

... SO Hi-Z Status Register & Write Protection The write protection features of the FM33256B are multi-tiered. To write the memory, a WREN op-code must first be issued, followed by a WRITE op-code. A Status Register associated with the memory has a write enable latch bit (WEL) that is internally set when WREN is issued ...

Page 23

... The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the F-RAM technology. Unlike SPI-bus EEPROMs, the FM33256B can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory begin with a WREN op- code with /CS being asserted and deasserted ...

Page 24

... Std JESD22-A114-E) (JEDEC Std JESD22-C101-C) (JEDEC Std JESD22-A115-A) = 2.7V to 3.6V unless otherwise specified) DD Min 2.7 1.55 1.90 =0V BAK 50 200 2.53 2.68 2.78 2. µ 1.6 2.0 -0.3 FM33256B SPI Companion w/ FRAM Ratings -1.0V to +5.0V -1.0V to +5.0V and V < V +1. -1.0V to +4.5V -55° 125°C 260° C TBD TBD TBD MSL-1 Typ Max Units Notes - 3.6 V ...

Page 25

... Does not apply to PFI, X1, or X2. IN OUT SS DD 12. Includes /RST input detection of external reset condition to trigger driving of /RST signal by FM33256B. AC Parameters (T = -40° 85° Symbol Parameter f SCK Clock Frequency CK t Clock High Time CH t ...

Page 26

... 100 0.3*t t DOG2 0 waveform. is the programmed EndTime in registers 0Bh and 0Ch, V DOG2 Min 10% and 90 0 FM33256B SPI Companion w/ FRAM Max Units Notes 100 pF Max Units Notes 100 ms 4 µ µs/V ...

Page 27

... SO VDD VTP VRST RST This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Rev. 3.0 Aug. 2012 FM33256B SPI Companion w/ FRAM ...

Page 28

... XXXX= part number, P= package type (-G) LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week FM33256B-G AL3902G RIC 1140 FM33256B SPI Companion w/ FRAM . . . 7.70 3. 0.65 0.19 45 0.25 0.40 1.27 Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com Page ...

Page 29

... Summary Initial release. Minor edits. Changed to Preliminary status. Added timing parameter for oscillator startup. Added Vtp data and changed to production status FM33256B SPI Companion w/ FRAM Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com Page ...

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