FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet - Page 7

• Manufacturer Part Number: FM33256B-G
• Description: Real Time Clock 256Kb F-RAM Processor Companion
• Manufacturer: Cypress Semiconductor

Specifications of FM33256B-G

• Rohs: yes
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Factory Pack Quantity: 56

Figure 8. Polled Mode on CNT pin Detects Tamper
The counter is nonvolatile when the NVC bit
(register 0Dh, bit 7) is logic 1 and battery-backed
when the NVC bit is logic 0. Setting the counter
mode to battery-backed allows counter operation
under V
operating voltage for battery-backed mode is 2.0V.
When set to “nonvolatile” mode, the counter operates
only when V
voltage.
The event counter may be programmed to detect a
tamper event, such as the system’s case or access
door being opened. A normally closed switch is tied
to the CNT pin and the other contact to the case
chassis, usually ground. The typical solution uses a
pullup resistor on the CNT pin and will continuously
draw battery current. The FM33256B chip allows the
user to invoke a polled mode, which occasionally
samples the pin in order to minimize battery drain. It
internally tries to pull the CNT pin up and if open
circuit will be pulled up to a V
the edge detector and increment the event counter
value. Setting the POLL bit (register 0Dh, bit 1)
places the CNT pin into this mode. This mode allows
the event counter to detect a rising edge tamper event
but the user is restricted to operating in battery-
backed mode (NVC=0) and using rising edge
detection (CP=1). The CNT pin is polled once every
125ms. The additional average I
than 20nA. The polling timer circuit operates from
the RTC, so the oscillator must be enabled for this to
function properly.
In the polled mode, the internal pullup circuit can
source a limited amount of current. The maximum
capacitance (switch open circuit) allowed on the CNT
pin is 100pF.
Serial Number
A memory location to write a 64-bit serial number is
provided. It is a writeable nonvolatile memory block
that can be locked by the user once the serial number
is set. The 8 bytes of data and the lock bit are all
accessed via unique op-codes for the RTC and
Processor Companion registers. Therefore the serial
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
< 100pF
BAK
CNT
(as well as V
DD
is applied and is above the V
Vbak
DD
125ms
IH
) power. The lowest
level, which will trip
BAK
FM33256B
current is less
TP
number area is separate and distinct from the memory
array. The serial number registers can be written an
unlimited number of times, so these locations are
general purpose memory. However once the lock bit
is set, the values cannot be altered and the lock
cannot be removed. Once locked the serial number
registers can still be read by the system.
The serial number is located in registers 10h to 17h.
The lock bit is SNL, register 18h bit 7. Setting the
SNL bit to a 1 disables writes to the serial number
registers, and the SNL bit cannot be cleared.
Alarm
The alarm function compares user-programmed
values to the corresponding time/date values and
operates under V
occurs, an alarm event occurs. The alarm drives an
internal flag AF (register 00h, bit 6) and may drive
the ACS pin, if desired, by setting the AL/SW bit
(register 18h, bit 6) in the Companion Control
register. The alarm condition is cleared by writing a
‘0’ to the AF bit.
There are five alarm match fields. They are Month,
Date, Hours, Minutes, and Seconds. Each of these
fields also has a Match bit that is used to determine if
the field is used in the alarm match logic. Setting the
Match bit to ‘0’ indicates that the corresponding field
will be used in the match process.
Depending on the Match bits, the alarm can occur as
specifically as one particular second on one day of
the month, or as frequently as once per second
continuously. The MSB of each Alarm register is a
Match bit. Examples of the Match bit settings are
shown in Table 3. Selecting none of the match bits
(all ‘1’s) indicates that no match is required. The
alarm occurs every second. Setting the match select
bit for seconds to ‘0’ causes the logic to match the
seconds alarm value to the current time of day. Since
a match will occur for only one value per minute, the
alarm occurs once per minute. Likewise setting the
seconds and minutes match select bits causes an
exact match of these values. Thus, an alarm will
occur once per hour. Setting seconds, minutes, and
hours causes a match once per day. Lastly, selecting
all match-values causes an exact time and date match.
Selecting other bit combinations will not produce
meaningful results, however the alarm circuit will
follow the functions described.
There are two ways a user can detect an alarm event,
by reading the AF flag or monitoring the ACS pin.
1850 Ramtron Drive, Colorado Springs, CO 80921
FM33256B SPI Companion w/ FRAM
DD
Ramtron International Corporation
or V
BAK
(800) 545-FRAM, [phone]
power. When a match
www.ramtron.com
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