FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet - Page 19

• Manufacturer Part Number: FM33256B-G
• Description: Real Time Clock 256Kb F-RAM Processor Companion
• Manufacturer: Cypress Semiconductor

Specifications of FM33256B-G

• Rohs: yes
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Factory Pack Quantity: 56

Serial Peripheral Interface – SPI Bus
The FM33256B employs a Serial Peripheral
Interface (SPI) bus. It is specified to operate at
speeds
16 MHz. This high-speed serial bus provides high
performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM33256B device operate in SPI Mode 0 and 3.
the bus master, the FM33256B will begin monitoring
the clock and data lines. The relationship between
the falling edge of /CS, the clock and data is dictated
by the SPI mode. The device will make a
determination of the SPI mode on the falling edge of
each chip select. While there are four such modes,
For a microcontroller that has no dedicated SPI bus,
a general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins together. Figure 14 shows
a configuration that uses only three pins.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
Figure 14. System Configuration without SPI port
Figure 13. System Configuration with SPI port
Microcontroller
MOSI: Master Out, Slave In
MISO: Master In, Slave Out
SS: Slave Select
Microcontroller
SPI
SCK
MOSI
MISO
SS1
SS2
SO
FM33256B
CS
up
SI SCK
SO
CS
FM33256B
SI
SO
SCK
FM25W256
CS
SI SCK
to
the FM33256B supports only modes 0 and 3. Figure
15 shows the required signal relationships for modes
0 and 3. For both modes, data is clocked into the
FM33256B on the rising edge of SCK and data is
expected on the first rising edge after /CS goes
active. If the clock starts from a high state, it will fall
prior to the first data transfer in order to create the
first rising edge.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses an FM33256B and a standalone
SPI device with a microcontroller that has a
dedicated SPI port, as Figure 13 illustrates. Note that
the clock, data-in, and data-out pins are common
among all devices. The /CS pins must be driven
separately for the FM33256B and each additional
SPI device.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the
SPI Mode 0: CPOL=0, CPHA=0
SPI Mode 3: CPOL=1, CPHA=1
Figure 15. SPI Modes 0 & 3
1850 Ramtron Drive, Colorado Springs, CO 80921
FM33256B SPI Companion w/ FRAM
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Ramtron International Corporation
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(800) 545-FRAM, [phone]
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www.ramtron.com
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