FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet - Page 20

• Manufacturer Part Number: FM33256B-G
• Description: Real Time Clock 256Kb F-RAM Processor Companion
• Manufacturer: Cypress Semiconductor

Specifications of FM33256B-G

• Rohs: yes
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Factory Pack Quantity: 56

bus master is the op-code. Following the op-code,
any addresses and data are then transferred. Note that
the WREN and WRDI op-codes are commands with
no subsequent data transfer.
Important: The /CS pin must go inactive after an
operation is complete and before a new op-code
can be issued. There is only one valid op-code per
active chip select.
Data Transfer
All data transfers to and from the FM33256B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are eight commands called op-codes that can
be issued by the bus master to the FM33256B. They
are listed in the table below. These op-codes control
the functions performed by the memory and
Processor Companion. They can be divided into
three categories. First, there are commands that have
no subsequent operations. They perform a single
function, such as, enabling a write operation. Second
are commands followed by one data byte, either in or
out. They operate on the Status Register. The third
group includes commands for memory and Processor
Companion transactions followed by address and
one or more bytes of data.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
Name
WREN
WRDI
Table 5. Op-code Commands
Description
Set Write Enable Latch
Write Disable
SCK
SO
CS
SI
0
0
Figure 16. WREN Bus Configuration
0
Op-code
0000 0110b
0000 0100b
1
0
2
0
Hi-Z
3
0
4
WREN – Set Write Enable Latch
The FM33256B will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the Status
Register, writing the Processor Companion, and
writing the memory.
Write Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the latch.
WEL=1
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit. The
WEL bit will automatically be cleared on the rising
edge of /CS following a WRDI, WRSR, WRPC, or
WRITE op-code. No other op-code affects the state
of the WEL bit. This prevents further writes to the
Status Register, F-RAM memory, or the companion
register space without another WREN command.
Figure 16 below illustrates the WREN command bus
configuration.
WRDI – Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the Status Register and verifying that WEL=0.
Figure 17 illustrates the WRDI command bus
configuration.
Sending the WREN op-code causes the internal
RDSR
WRSR
READ
WRITE
RDPC
WRPC
1
5
indicates
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
Read Proc. Companion
Write Proc. Companion
1850 Ramtron Drive, Colorado Springs, CO 80921
FM33256B SPI Companion w/ FRAM
1
6
Ramtron International Corporation
0
7
that
(800) 545-FRAM, [phone]
writes
are
www.ramtron.com
0000 0101b
0000 0001b
0000 0011b
0000 0010b
0001 0011b
0001 0010b
permitted.
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