FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet - Page 6

• Manufacturer Part Number: FM33256B-G
• Description: Real Time Clock 256Kb F-RAM Processor Companion
• Manufacturer: Cypress Semiconductor

Specifications of FM33256B-G

• Rohs: yes
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Factory Pack Quantity: 56

Note the internal weak pull-up eliminates the need
for additional external components.
Reset Flags
In case of a reset condition, a flag bit will be set to
indicate the source of the reset. A low-V
indicated by the POR bit, register 09h bit 5. There are
two watchdog reset flags - one for an early fault
(EWDF) and the other for a late fault (LWDF),
located in register 09h bits 7 and 6. A manual reset
will result in no flag being set, so the absence of a
flag is a manual reset. Note that the bits are set in
response to reset sources but they must be cleared by
the user. It is possible to read the register and have
both sources indicated if both have occurred since the
user cleared them.
Power Fail Comparator
An analog comparator compares the PFI input pin to
an onboard 1.5V reference. When the PFI input
voltage drops below this threshold, the comparator
will drive the PFO pin to a low state. The comparator
has 100 mV of hysteresis (rising voltage only) to
reduce
application of this comparator is to create an early
warning power fail interrupt (NMI). This can be
accomplished by connecting the PFI pin to an
upstream power supply via a resistor divider. An
application circuit is shown below. The comparator is
a general purpose device and its application is not
limited to the NMI function.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
Behavior
Switch
RST
MCU
noise
Switch
Reset
Figure 5. Manual Reset
sensitivity.
FM33256B
drives
RST
100 ms (max.)
FM33256B
The
most
DD
common
reset is
If the power-fail comparator is not used, the PFI pin
should be tied to either V
PFO output will drive to V
Event Counter
The FM33256B offers the user a nonvolatile 16-bit
event
programmable edge detector. The CNT pin clocks the
counter. The counter is located in registers 0E-0Fh.
When the programmed edge polarity occurs, the
counter will increment its count value. The register
value is read by setting the RC bit (register 0Dh, bit
3) to 1. This takes a snapshot of the counter byte
allowing a stable value even if a count occurs during
the read. The register value can be written by first
setting the WC bit (register 0Dh, bit 2) to 1. The user
then may clear or preset the counter by writing to
registers 0E-0Fh. Counts are blocked when the WC
bit is set, so the user must clear the bit to allow
counts.
The counter polarity control bit is CP, register 0Dh
bit 0. When CP is 0, the counter increments on a
falling edge of CNT, and when CP is set to 1, the
counter increments on a rising edge of CNT. The
polarity bit CP is nonvolatile.
The counter does not wrap back to zero when it
reaches the limit of 65,535 (FFFFh). Care must be
taken prior to the rollover, and a subsequent counter
reset operation must occur to continue counting.
There is also a control bit that allows the user to
define the counter as nonvolatile or battery-backed.
CNT
NMI input
To MCU
Figure 6. Comparator as a Power-Fail Warning
counter.
PFO
CP
1850 Ramtron Drive, Colorado Springs, CO 80921
FM33256B SPI Companion w/ FRAM
Figure 7. Event Counter
FM33256B
The
+
-
Ramtron International Corporation
1.5V ref
input
(800) 545-FRAM, [phone]
DD
DD
or V
or V
Regulator
pin
16-bit Counter
SS
SS
as well.
www.ramtron.com
. Note that the
CNT
VDD
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has
a