FM33256B-G Cypress Semiconductor, FM33256B-G Datasheet - Page 8

• Manufacturer Part Number: FM33256B-G
• Description: Real Time Clock 256Kb F-RAM Processor Companion
• Manufacturer: Cypress Semiconductor

Specifications of FM33256B-G

• Rohs: yes
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Factory Pack Quantity: 56

The interrupt pin on the host processor may be used
to detect an alarm event. The AF flag in register 00h
(bit 6) will indicate that a time/date match has
occurred. The AF flag will be set to ‘1’ when a match
occurs. The AEN bit must be set to enable the AF
flag on alarm matches. The flag and ACS pin will
remain in this state until the AF bit is cleared by
writing it to a ‘0’. Clearing the AEN bit will prevent
further matches from setting AF but will not
automatically clear the AF flag.
The RTC alarm is integrated into the special function
registers and shares its output pin with the 512Hz
calibration and square wave outputs. When the RTC
calibration mode is invoked by setting the CAL bit
(register 00h, bit 2), the ACS output pin will be
driven with a 512 Hz square wave and the alarm will
continue to operate. Since most users only invoke the
calibration mode during production this should have
no impact on the otherwise normal operation of the
alarm.
Table 3. Alarm Match Bit Examples
Real-time Clock Operation
The real-time clock (RTC) is a timekeeping device
that can be capacitor- or battery-backed for
permanently-powered operation. It offers a software
calibration feature that allows high accuracy.
The RTC consists of an oscillator, clock divider, and
a register system for user access. It divides down the
32.768 kHz time-base and provides a minimum
resolution of seconds (1Hz). Static registers provide
the user with read/write access to the time values. It
includes registers for seconds, minutes, hours, day-
of-the-week, date, months, and years. A block
diagram shown in Figure 9 illustrates the RTC
function.
The user registers are synchronized with the
timekeeper core using R and W bits in register 00h.
The R bit is used to read the time. Changing the R bit
from 0 to 1 transfers timekeeping information from
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.0
Aug. 2012
Seconds
1
0
0
0
0
Minutes
1
1
0
0
0
Hours
1
1
1
0
0
Date
1
1
1
1
0
Months
1
1
1
1
1
Alarm condition
No match required = alarm 1/second
Alarm when seconds match = alarm 1/minute
Alarm when seconds, minutes match = alarm 1/hour
Alarm when seconds, minutes, hours match = alarm 1/date
Alarm when seconds, minutes, hours, date match = alarm 1/month
The ACS output may also be used to drive the system
with a frequency other than 512 Hz. The AL/SW bit
(register 18h, bit 6) must be ‘0’. A user-selectable
frequency is provided by F0 and F1 (register 18h, bits
4 and 5). The other frequencies are 1, 4096, and
32768 Hz.
enabled with CAL mode, the alarm function will not
be available.
Following is a summary table that shows the
relationship between register control settings and the
state of the ACS pin.
the core into the user registers 02-08h that can be
read by the user. If a timekeeper update is pending
when R is set, then the core will be updated prior to
loading the user registers. The user registers are
frozen and will not be updated again until the R bit is
cleared to a ‘0’.
The W bit is used to write new time/date values.
Setting the W bit to a ‘1’ stops the RTC and allows
the timekeeping core to be written with new data.
Clearing it to ‘0’ causes the RTC to start running
based on the new values loaded in the timekeeper
core. The RTC may be synchronized to another clock
source. On the 8
(W=0), the RTC starts counting with a timebase that
has been reset to zero milliseconds.
Note: Users should be certain not to load invalid
values, such as FFh, to the timekeeping registers.
Updates to the timekeeping core occur continuously
except when locked.
CAL
State of Register Bit
0
0
1
0
Table 2. State of Register Bit
1850 Ramtron Drive, Colorado Springs, CO 80921
FM33256B SPI Companion w/ FRAM
If a continuous frequency output is
AEN
th
X
X
1
0
clock of the write to register 00h
Ramtron International Corporation
AL/SW
X
(800) 545-FRAM, [phone]
1
0
1
Sq Wave out
Function of
512 Hz out
ACS pin
/Alarm
www.ramtron.com
Hi-Z
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