MC9S12P32MFT Freescale Semiconductor, MC9S12P32MFT Datasheet - Page 248

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MC9S12P32MFT

Manufacturer Part Number
MC9S12P32MFT
Description
16-bit Microcontrollers - MCU 16 BIT 32K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC9S12P32MFT

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
32 MHz
Program Memory Size
32 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
S12 Clock, Reset and Power Management Unit (S12CPMU)
Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to
the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out
period. A premature write will immediately reset the part.
7.5.3
The on-chip POR circuitry detects when the internal supply V
(voltage level not specified in this document because this supply is not visible on device pins). POR is
deasserted, if the internal supply V
this document because this supply is not visible on device pins).
7.5.4
The on-chip LVR circuitry detects when one of the supply voltages V
appropriate voltage level. If LVR is deasserted the MCU is fully operational at the specified maximum
speed.The LVR assert and deassert levels for the supply voltage VDDX are V
specified in the device Reference Manual.
7.6
The interrupt/reset vectors requested by the S12CPMU are listed in
specification for related vector addresses and priorities.
248
Interrupts
Power-On Reset (POR)
Low-Voltage Reset (LVR)
RTI time-out interrupt
Low voltage interrupt
Interrupt Source
Periodical Interrupt
PLL lock interrupt
High temperature
Oscillator status
Autonomous
interrupt
interrupt
Table 7-27. S12CPMU Interrupt Vectors
S12P-Family Reference Manual, Rev. 1.13
DD
exceeds an appropriate voltage level (voltage level not specified in
Mask
CCR
I bit
I bit
I bit
I bit
I bit
I bit
CPMUAPICTL (APIE)
CPMUHTCTL (HTIE)
CPMUINT (LOCKIE)
CPMULVCTL (LVIE)
CPMUINT (OSCIE)
CPMUINT (RTIE)
DD
Local Enable
drops below an appropriate voltage level
Table
DD
, V
7-27. Refer to MCU
DDF
LVRXA
or V
Freescale Semiconductor
and V
DDX
drops below an
LVRXD
and are

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