MC9S12P32MFT Freescale Semiconductor, MC9S12P32MFT Datasheet - Page 310

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MC9S12P32MFT

Manufacturer Part Number
MC9S12P32MFT
Description
16-bit Microcontrollers - MCU 16 BIT 32K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC9S12P32MFT

Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
32 MHz
Program Memory Size
32 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
Analog-to-Digital Converter (ADC12B10C)
9.3.2
This section describes in address order all the ADC12B10C registers and their individual bits.
9.3.2.1
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
310
Address
0x0024 -
Module Base + 0x0000
0x002F
0x0020
0x0022
WRAP[3-0]
Reset
Field
3-0
W
R
Reserved
Unimple-
ATDDR8
ATDDR9
mented
Name
Register Descriptions
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-
channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
7
WRAP3 WRAP2 WRAP1 WRAP0
0
0
0
0
0
0
= Unimplemented or Reserved
W
W
W
R
R
R
Figure 9-2. ADC12B10C Register Summary (Sheet 3 of 3)
0
0
6
Bit 7
0
0
0
0
1
1
0
Table 9-2. Multi-Channel Wrap Around Coding
Figure 9-3. ATD Control Register 0 (ATDCTL0)
Table 9-1. ATDCTL0 Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
= Unimplemented or Reserved
0
0
1
1
0
0
0
0
5
0
6
and
and
See
See
Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
0
1
0
1
0
1
5
0
0
0
4
Multiple Channel Conversions (MULT = 1)
Description
Wraparound to AN0 after Converting
Table
0
4
WRAP3
9-2.
1
3
Reserved
3
0
AN1
AN2
AN3
AN4
AN5
WRAP2
(1)
1
2
2
0
WRAP1
Freescale Semiconductor
1
1
1
0
WRAP0
Bit 0
1
0
0

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