S9S12G64F0MLH Freescale Semiconductor, S9S12G64F0MLH Datasheet - Page 1080
S9S12G64F0MLH
Manufacturer Part Number
S9S12G64F0MLH
Description
16-bit Microcontrollers - MCU S12 Core,64k Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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128 KByte Flash Module (S12FTMRG128K1V1)
29.4.7
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an ECC fault.
29.4.7.1
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with
the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed
description of the register bits involved, refer to
(FCNFG)”,
Status Register
The logic used for generating the Flash module interrupts is shown in
1082
Flash Command Complete
ECC Double Bit Fault on Flash Read
ECC Single Bit Fault on Flash Read
Section 29.3.2.6, “Flash Error Configuration Register
Interrupts
Description of Flash Interrupt Operation
Vector addresses and their relative interrupt priority are determined at the
MCU level.
(FSTAT)”, and
Interrupt Source
DFDIE
DFDIF
SFDIE
SFDIF
CCIE
CCIF
Figure 29-27. Flash Module Interrupts Implementation
Section 29.3.2.8, “Flash Error Status Register
MC9S12G Family Reference Manual,
Table 29-66. Flash Interrupt Sources
(FERSTAT register)
(FERSTAT register)
(FSTAT register)
Interrupt Flag
DFDIF
SFDIF
Section 29.3.2.5, “Flash Configuration Register
CCIF
NOTE
Flash Command Interrupt Request
Flash Error Interrupt Request
(FERCNFG register)
(FERCNFG register)
(FCNFG register)
(FERCNFG)”,
Rev.1.23
Local Enable
DFDIE
SFDIE
CCIE
Figure
29-27.
(FERSTAT)”.
Section 29.3.2.7, “Flash
Freescale Semiconductor
Global (CCR)
Mask
I Bit
I Bit
I Bit
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