S9S12G64F0MLH Freescale Semiconductor, S9S12G64F0MLH Datasheet - Page 388
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S9S12G64F0MLH
Manufacturer Part Number
S9S12G64F0MLH
Description
16-bit Microcontrollers - MCU S12 Core,64k Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.13 Low Voltage Control Register (CPMULVCTL)
The CPMULVCTL register allows the configuration of the low-voltage detect features.
Read: Anytime
Write: LVIE and LVIF are write anytime, LVDS is read only
390
0x02F1
The Reset state of LVDS and LVIF depends on the external supplied VDDA level
Reset
LVDS
Field
LVIE
LVIF
2
1
0
W
R
Low-Voltage Detect Status Bit — This read-only status bit reflects the voltage level on VDDA. Writes have no
effect.
0 Input voltage VDDA is above level V
1 Input voltage VDDA is below level V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
0
0
7
= Unimplemented or Reserved
Figure 10-16. Low Voltage Control Register (CPMULVCTL)
0
0
6
Table 10-15. CPMULVCTL Field Descriptions
MC9S12G Family Reference Manual,
0
0
5
LVIA
LVID
and FPM.
or RPM.
0
0
4
Description
0
0
3
Rev.1.23
LVDS
U
2
Freescale Semiconductor
LVIE
0
1
LVIF
U
0
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