S9S12G64F0MLH Freescale Semiconductor, S9S12G64F0MLH Datasheet - Page 172
S9S12G64F0MLH
Manufacturer Part Number
S9S12G64F0MLH
Description
16-bit Microcontrollers - MCU S12 Core,64k Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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Port Integration Module (S12GPIMV1)
174
PT4
PT3-PT2
PT1
PT0
• 48/64/100 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function.
• Signal priority:
• Except 20 TSSOP: The TIM channels 3 and 2 signal are mapped to these pins when used with the
• Signal priority:
• Except 100 LQFP: The IRQ signal is mapped to this pin when used with the IRQ interrupt function. If
• The TIM channel 1 signal is mapped to this pin when used with the timer function. The TIM forces the
• Signal priority:
• Except 100 LQFP: The XIRQ signal is mapped to this pin when used with the XIRQ interrupt
• The TIM channel 0 signal is mapped to this pin when used with the timer function. The TIM forces the
• Signal priority:
The TIM forces the I/O state to be an output for a timer port associated with an enabled output
compare.
48/64/100 LQFP: IOC4 > GPO
timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled
output compare.
Except 20 TSSOP: IOC3-2 > GPO
enabled (IRQCR[IRQEN]=1) the I/O state of the pin is forced to be an input.
I/O state to be an output for a timer port associated with an enabled output compare.
100 LQFP: IOC1 > GPO
Others: IRQ > IOC1 > GPO
function.The interrupt is enabled by clearing the X mask bit in the CPU Condition Code register. The
I/O state of the pin is forced to input level upon the first clearing of the X bit and held in this state even
if the bit is set again. A STOP or WAIT recovery with the X bit set (refer to CPU12/CPU12X Reference
Manual) is not available.
I/O state to be an output for a timer port associated with an enabled output compare.
100 LQFP: IOC0 > GPO
Others: XIRQ > IOC0 > GPO
Table 2-11. Port
MC9S12G Family Reference Manual,
T
Pins PT7-0 (continued)
Rev.1.23
Freescale Semiconductor
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